Maximum circuit activity estimation using pseudo-boolean satisfiability

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 1538-1543

  Mangassarian, Hratch ^a   Veneris, Andreas ^a   Safarpour, Sean ^a   Najm, Farid N ^a   Abadir, Magdy S ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; MICROPROCESSOR CHIPS; OPTIMIZATION; VLSI CIRCUITS;

BOOLEAN SATISFIABILITY; POWER SUPPLY VOLTAGE FLUCTUATIONS; PSEUDO-BOOLEAN OPTIMIZATION;

ENERGY DISSIPATION;

EID: 34548336658     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364519     Document Type: Conference Paper

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