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Volumn , Issue , 2007, Pages 319-324

Design space exploration of partially re-configurable embedded processors

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT MANUFACTURE; RESOURCE ALLOCATION;

EID: 34548316215     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364611     Document Type: Conference Paper
Times cited : (14)

References (20)
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    • Stretch, http://www.stretchinc.com.
    • Stretch1
  • 6
    • 34548353586 scopus 로고    scopus 로고
    • Target Compiler Technologies
    • Target Compiler Technologies, http://www.retarget.com.
  • 7
    • 85008025144 scopus 로고    scopus 로고
    • A. Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink, and H. Meyr, A Novel Methodology for the Design of Application Specific Instruction-Set Processor Using a Machine Description Language, in IEEE Transactions on Computer-Aided Design of Integrated Cicuits and Systems (TCAD) 20 no. 11, pp. 1338-1354, IEEE, 2001.
    • A. Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink, and H. Meyr, "A Novel Methodology for the Design of Application Specific Instruction-Set Processor Using a Machine Description Language," in IEEE Transactions on Computer-Aided Design of Integrated Cicuits and Systems (TCAD) vol. 20 no. 11, pp. 1338-1354, IEEE, 2001.
  • 8
    • 0036709503 scopus 로고    scopus 로고
    • Reconfigurable instruction set processors from a hardware/software perspective
    • F. Barat, R. Lauwereins, and G. Deconinck, "Reconfigurable instruction set processors from a hardware/software perspective," IEEE Trans. Softw. Eng., vol. 28, no. 9, pp. 847-862, 2002.
    • (2002) IEEE Trans. Softw. Eng , vol.28 , Issue.9 , pp. 847-862
    • Barat, F.1    Lauwereins, R.2    Deconinck, G.3
  • 15
    • 33746904375 scopus 로고    scopus 로고
    • ISEGEN: An Iterative Improvement-based ISE Generation Technique for Fast Customization of Processors
    • P. Biswas, S. Banerjee, N. Dutt, L. Pozzi and P. Ienne, "ISEGEN: an Iterative Improvement-based ISE Generation Technique for Fast Customization of Processors," IEEE Transactions on VLSI Systems, vol. 14, no. 7, 2006.
    • (2006) IEEE Transactions on VLSI Systems , vol.14 , Issue.7
    • Biswas, P.1    Banerjee, S.2    Dutt, N.3    Pozzi, L.4    Ienne, P.5
  • 17
    • 34047130293 scopus 로고    scopus 로고
    • A Design Flow for Configurable Embedded Processors based on Optimized Instruction Set Extension Synthesis
    • R. Leupers, K. Karuri, S. Kraemer and M. Pandey, "A Design Flow for Configurable Embedded Processors based on Optimized Instruction Set Extension Synthesis," in Design, Automation & Test in Europe (DATE), 2006.
    • (2006) Design, Automation & Test in Europe (DATE)
    • Leupers, R.1    Karuri, K.2    Kraemer, S.3    Pandey, M.4
  • 18
    • 34548343655 scopus 로고    scopus 로고
    • Synopsys, http://www.synopsys.com.
    • Synopsys1
  • 19
    • 34548368208 scopus 로고    scopus 로고
    • Xilinx, Virtex-II pro http://www.xilinx.com/products/ silicon_solutions/fpgas/.
    • Virtex-II pro
    • Xilinx1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.