Shared transistor architecture with diagonally connected pixels for CMOS image sensors

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6501, Issue , 2007, Pages

  Kudoh, Yoshiharu ^a   Koga, Fumihiko ^a   Abe, Takashi ^a   Taniguchi, Haruyuki ^a   Sato, Maki ^a   Ishiwata, Hiroaki ^a   Ooki, Susumu ^a   Suzuki, Ryoji ^a   Mori, Hiroyuki ^a  

^a SONY CORPORATION   (Japan)

Author keywords

CMOS image sensor; Pixel; Shared transistor architecture

Indexed keywords

ALUMINUM; AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); PHOTODIODES; PIXELS;

SHARED TRANSISTOR ARCHITECTURES;

IMAGE SENSORS;

EID: 34548266110     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.704835     Document Type: Conference Paper

References (3)

1. M. Mori, et al., "A 1/4 inch 2M pixel CMOS Image Sensor with 1.75 Transistor/Pixel," ISSCC Dig. Tech. Papers, pp. 110-111, Feb. 2004.
2. Y. Kim, et al., "1/2-inch 7.2MPixel CMOS Image Sensor with 2.25μm Pixels Using 4-Shared Pixel Structure for Pixel-Level Summation," ISSCC Dig. Tech. Papers, pp. 494-495, Feb. 2006.
3. S.Yoshihara, et al., "A 1/1.8-inch 6.4MPixel 60 frames/s CMOS Image Sensor with Seamless Mode Change," ISSCC Dig. Tech. Parers, pp. 492-493, Feb. 2006.