High performance implementation of tridiagonalization on the SR8000

Proceedings - 4th International Conference/Exhibition on High Performance Computing in the Asia-Pacific Region, HPC-Asia 2000

Volumn 1, Issue , 2000, Pages 206-219

  Naono, K ^a   Yamamoto, Y ^a   Igai, M ^a   Hirayama, H ^a  

^a HITACHI LTD   (Japan)

Author keywords

byte flop; hybrid architecture; SR8000; tridiagonalization

Indexed keywords

COMPUTER PROGRAMMING; COMPUTER SCIENCE;

BYTE/FLOP; HIGH PERFORMANCE IMPLEMENTATIONS; HYBRID ARCHITECTURES; PEAK PERFORMANCE; READ/WRITE OPERATIONS; REAL SYMMETRIC MATRIX; SR8000; TRIDIAGONALIZATION;

MATRIX ALGEBRA;

EID: 34548252153     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPC.2000.846547     Document Type: Conference Paper

References (8)

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