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Volumn , Issue , 2007, Pages 920-924

Topology and binary routing schemes of a PRDT-based NoC

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; TOPOLOGY; VIRTUAL REALITY;

EID: 34548120302     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITNG.2007.195     Document Type: Conference Paper
Times cited : (6)

References (13)
  • 1
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Jan
    • L. Benini and G.D. Mioheli, "Networks on chips: a new SoC paradigm," IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
    • (2002) IEEE Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    Mioheli, G.D.2
  • 3
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not Wires: On-chip interconnection networks
    • W.J. Dally, B. Towles, "Route packets, not Wires: on-chip interconnection networks," Proc. Design Automation Conf (DAC), 2001, pp. 684-689.
    • (2001) Proc. Design Automation Conf (DAC) , pp. 684-689
    • Dally, W.J.1    Towles, B.2
  • 4
    • 0023346637 scopus 로고
    • Deadlock-free message routing in multiprocessor interconnection networks
    • May
    • W.J. Dally, C.L. Seitz, "Deadlock-free message routing in multiprocessor interconnection networks," IEEE Trans. Computers, vol. 36, no. 5, pp. 547-553, May 1987.
    • (1987) IEEE Trans. Computers , vol.36 , Issue.5 , pp. 547-553
    • Dally, W.J.1    Seitz, C.L.2
  • 5
    • 0027837827 scopus 로고
    • A new theory of deadlock-free adaptive routing in wormhole networks
    • Sept
    • J. Duato, "A new theory of deadlock-free adaptive routing in wormhole networks," IEEE Trans. Parallel and Distributed Systems, vol. 4, no. 12, pp. 1320-1331, Sept. 1995.
    • (1995) IEEE Trans. Parallel and Distributed Systems , vol.4 , Issue.12 , pp. 1320-1331
    • Duato, J.1
  • 7
    • 0036760609 scopus 로고    scopus 로고
    • A scalable high-performance computing solution for networks on chips
    • Sept
    • M. Forsell, "A scalable high-performance computing solution for networks on chips," IEEE Micro., vol. 22, no. 5, pp. 46-55, Sept. 2002.
    • (2002) IEEE Micro , vol.22 , Issue.5 , pp. 46-55
    • Forsell, M.1
  • 8
    • 84893687806 scopus 로고    scopus 로고
    • A generic architecture for on chip packetswitched interconnections
    • P. Guerrier, A. Greiner, "A generic architecture for on chip packetswitched interconnections," Proc. DATE, 2000, pp. 250-256.
    • (2000) Proc. DATE , pp. 250-256
    • Guerrier, P.1    Greiner, A.2
  • 10
    • 34548117514 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors ITRS, available at
    • International Technology Roadmap for Semiconductors (ITRS), available at http://public.itrs.net/Files/2005ITRS/Home2005.htm.
  • 13
    • 33846987632 scopus 로고    scopus 로고
    • A RDT-based interconnection network for scalable NoC designs
    • Y. Yu, M. Yang, Y. Yang, and Y. Jiang, "A RDT-based interconnection network for scalable NoC designs," Proc. IEEE ITCC, 2005, pp. 729-734.
    • (2005) Proc. IEEE ITCC , pp. 729-734
    • Yu, Y.1    Yang, M.2    Yang, Y.3    Jiang, Y.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.