Reconfigurable OPB coprocessors for a microblaze self-reconfigurable SOC mapped on spartan-3 FPGAs

IECON Proceedings (Industrial Electronics Conference)

Volumn , Issue , 2006, Pages 4940-4944

  Cantó, Enrique ^a   Fons, Francesc ^a   López, Mariano ^b  

^a UNIVERSITAT ROVIRA I VIRGILI   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRONICS INDUSTRY; INDUSTRIAL ELECTRONICS; INTEGRATED CIRCUITS; MAPS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS;

ANNUAL CONFERENCE; CO-PROCESSORS; CONFIGURATION MEMORY; EXTERNAL-; FPGA DEVICES; ON-CHIP PERIPHERAL BUS; RE-CONFIGURABLE; RECONFIGURABLE CO-PROCESSORS; RECONFIGURABLE SOC; RUN-TIME; SPARTAN-3; SYSTEM-ON-CHIP; TIME-CRITICAL TASKS; TIME-MULTIPLEXED;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34547995546     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IECON.2006.347730     Document Type: Conference Paper

References (7)

1. IBM, "On-Chip Peripheral Bus. Architecture Specifications. Version 2.1",CoreConnect, The system on a chip bus standard, 2000
2. Xilinx, Spartan-3 Advanced Configuration Architecture, XAPP452 (v1.0), Dec. 2004
3. Xilinx, "ICAP_VIRTEX2", ISE 6.3i Libraries Guide, pp. 641-642, 2004
4. Xinlinx, Two Flows for Partial Reconfiguration: Module Based or Difference Based, XAPP290 (v 1.2), Sept. 2004
5. Xilinx, Spartan-3 Complete Data Sheet (v 2.0), Mar. 2006
6. I. Gonzalez, E. Aguayo, S. López Ubedo, "Sistemas Embedidos Auto-Reconfigurables sobre Spartan-3", in the V Jornadas de Computación Reconfigurable y Aplicaciones (JCRA'2005), pp.79-84, Sept. 2005
7. Xilinx, "Modular Designs (Chapter 4)", ISE 6.3i Development System Reference Guide, pp. 81-118, 2004.