Evaluating dataflow and pipelined vector processing architectures for FPGA co-processors

Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

Volumn , Issue , 2006, Pages 127-130

  Freeman, Michael ^a  

^a UNIVERSITY OF YORK   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DATA FLOW ANALYSIS; PIPELINE PROCESSING SYSTEMS; PROGRAM PROCESSORS;

EUCLIDEAN DISTANCE; PIPELINED VECTOR PROCESSING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34547983830     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2006.51     Document Type: Conference Paper

References (2)

1. Watson, I., Gurd, J.R., 1979, A Prototype Dataflow Computer with Token Labeling, AFIPS Proceedings, 48, 623-628
2. Xilinx, (2006), Floating-point Operator v2.0 WEB:http://www.xilinx. com/bvdocs/ipcenter/data_sheet/floating_point_ds335.pdf