Multi-bank main memory architecture with dynamic voltage frequency scaling for system energy optimization

Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

Volumn , Issue , 2006, Pages 89-96

  Ben Fradj, Hanene ^a   Belleudy, Cécile ^a   Auguin, Michel ^a  

^a UNIVERSITY OF NICE SOPHIA ANTIPOLIS   (France)

Author keywords

DVFS; Energy; Multi bank main memory; Multi task; Real time; System level

Indexed keywords

ELECTRIC POWER UTILIZATION; ENERGY CONSERVATION; MULTITASKING; REAL TIME SYSTEMS;

DYNAMIC VOLTAGE FREQUENCY SCALING; ENERGY OPTIMIZATION; MEMORY ARCHITECTURE; MULTI-BANK MAIN MEMORY;

DATA STORAGE EQUIPMENT;

EID: 34547977544     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2006.68     Document Type: Conference Paper

References (24)

1. W. Kim, J. Kim, and S. L. Min. "Quantitative Analysis of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems", In Proc. SoC Design Conference, November 2003.
2. ITRS roadmap.
3. X. Fan, C. S. Ellis, A. R. Lebeck "The Synergy between Power-aware Memory Systems and Processor Voltage Scaling" In Proc. PACS, 2003.
4. K. Choi, R. Soma, M. Pedram "Dynamic Voltage and Frequency Scaling based on Workload Decomposition" In Proc. ISLPED, August 2004.
5. W. Kim, J. Kim, S. L. Min "Preemption-aware dynamic voltage scaling in hard real-time systems", In Proc. ISLPED, August 2004, pp 393-398.
6. W. Kim, J. Kim, S. L. Min "Dynamic Voltage Scaling Algorithm for Fixed-Priority Real-Time Systems Using Work Demand Analysis" In Proc. ISLPED, 2003, pp 396-401.
7. R. Jejurikar, R. K. Gupta "Integrating Processor Slowdown and Preemption Threshold Scheduling for Energy Efficiency in Real Time Embedded Systems" In Proc. RTCSA, 2004.
8. F. Zhang and S. Chanson, "Blocking-Aware Processor Voltage Scheduling for Real-Time Tasks ", ACM Transaction on Embedded Computing Systems, Vol.3, Issue 2, pp. 307-335, May 2004.
9. 128/144 MBit Direct RDRAM Data Sheet, Rambus Inc. 1999.
10. Mobile-RAM Data Sheet, Infineon Inc, 2004
11. M. Kandemir, I. Kolcu and I. Kadayif "Influence of loop optimizations on energy consumption of multi-bank memory systems" In Proc. Compiler Construction, April 2002.
12. M. Mamidipaka, N Dutt "eCACTI: An Enhanced Power Estimation Model for On-chip Caches" Center for Embedded Computer Systems (CECS) Technical Report TR-04-28, September 2004.
13. PXA 270 Data Sheet, Intel Inc, 2005.
14. Y. Shin, K. Choi, and T. Sakurai "Power Optimization of Real-Time Embedded Systems on Variable Speed Processors" In Proc. ICCAD, 2000, pp. 365-368.
15. V. Delaluz, M. Kandemir, and I. Kolcu, "Automatic Data Migration for Reducing Energy Consumption in Multi-Bank Memory Systems", In Proc. DAC, 2002.
16. A. R Lebeck, X. Fan, H. Zeng and C. Ellis "Power Aware Page Allocation", In Proc. ASPLOS 2000, 2000.
17. O. Ozturk, M. Kandemir "Nonuniform banking for reducing memory energy consumption", In Proc. DATE 2005, 2005.
18. L. Benini, A. Macci, M, Poncino "A recursive algorithm for low-power memory partitioning" In Proc. ISLPED 2000, 2000.
19. V. Delaluz, M. Kandemir, U. Sezer "Improving Off-Chip Memory Energy Behavior in a Multi-processor, Multi-bank Environment". In Proc. LCPC 2001, pp 100-114.
20. K. Itoh, K. Sasaki and Y. Nakagome, "Trends in Low-Power RAM Circuit Technologies" Proc. IEEE, vol. 83, no. 4, April 1995, pp. 524-543.
21. V. Delaluz, M. Kandemir, N.Vijaykrishnan, A. Sivasubramaniam, M.J Irwin "DRAM Energy Management Using Software and Hardware Directed Power Mode Control". In Proc. HPCA, 2001 pp.159-170.
22. Seoul National University Real-Time Research Groups. SNU real-time benchmarks. http://archi.snu.ac.kr/realtime/benchmark/
23. D. Burger and T.M. Austin, "The SimpleScalar Tool Set, Version 2.0," Univ. of Wisconsin-Madison Computer Sciences Dept. Technical Report #1342, June 1997.
24. A. Agarwal, J. Hennessy, M. Horowitz "An analytical cache model" ACM Transactions on Computer Systems (TOCS), Vol. 7, Issue 2, May 1989, pp 184-215.