Analysis of writing and erasing procedure of flotox eeprom using the New Charge Balance Condition (CBC) model

Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, NUPAD 1992

Volumn , Issue , 1992, Pages 65-69

  Sugino, Satoshi ^a   Takakura, Nobuyuki ^a   Chen, Datong ^b   Button, Robert W ^b  

^a PANASONIC CORPORATION   (Japan)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; POISSON DISTRIBUTION; POISSON EQUATION; SILICON COMPOUNDS;

CHARGE BALANCES; EEPROM CELLS; FLOATING GATES; MODEL PARAMETERS; QUASI-STATIONARY; SI LAYER; SINGLE-POLY; THRESHOLD SHIFTS;

NUMERICAL MODELS;

EID: 34547867521     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NUPAD.1992.673848     Document Type: Conference Paper

References (5)

1. A.Bhattacharyya, 'Modeling of Write/Erase and Charge Retention Characteristics of Floating Gate EEPROM Devices', Solid-State Electrinics, Vol.27, pp.899-906, 1984.
2. C.Fiegna, F.Venturi, M.Melanotte, E.Sangiorgi and B.Ricco, 'Simple and Efficient Modeling of EPROM Writing', IEEE Trans, on Electron Devices, Vol.38, No. 3, pp.603-610, Mar. 1991.
3. B.Eitan and D.Frohman-Bentchkowsky, 'Hot-Electron Injection into Oxide in N-Channel MOS Devices', IEEE Trans, on Electron Devices, Vol.28, No.3 pp. 328-340, Mar.1991.
4. R.C.Wijburg, G.J.IIemink, J.Middlelhoek, H.Wallinga and T.J.Mouthaan, 'VIPMOS a Novel Buried Injector Structure for EPROM Applications', IEEE Trans, on Electron Devices, Vol.38, No. 1, pp. 111-120, Jan. 1991.
5. A.Kolondy et al. 'Analysis and Modeling of Floating Gate EEPROM Cells' IEEEED., Vol. ED33, No.6, June. 1986.