Yield learning and process optimization on 65-nm CMOS technology accelerated by the use of short flow test die

IEEE Transactions on Semiconductor Manufacturing

Volumn 20, Issue 3, 2007, Pages 201-207

  DeBord, Jeffrey R D ^a   Sridhar, Nagarajan ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

Design for manufacturability (DFM); Short flow test die; Yield optimization; Yield ramp

Indexed keywords

DIELECTRIC PROPERTIES; MICROPROCESSOR CHIPS; OPTIMIZATION; PROCESS CONTROL; SHORT CIRCUIT CURRENTS;

DESIGN FOR MANUFACTURABILITY (DFM); SHORT FLOW TEST DIE; YIELD OPTIMIZATION; YIELD RAMP;

CMOS INTEGRATED CIRCUITS;

EID: 34547813593     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2007.901825     Document Type: Conference Paper

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