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Volumn 2007, Issue , 2007, Pages

A framework for system-level modeling and simulation of embedded systems architectures

Author keywords

[No Author keywords available]

Indexed keywords


EID: 34547791862     PISSN: 16873955     EISSN: 16873963     Source Type: Journal    
DOI: 10.1155/2007/82123     Document Type: Article
Times cited : (57)

References (31)
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    • cagkan@science.uva.nl andy@science.uva.nl spolstra@science.uva.nl
    • A. D. Pimentel andy@science.uva.nl C. Erbas cagkan@science.uva.nl S. Polstra spolstra@science.uva.nl A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Transactions on Computers 55 2 2006 99 112
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  • 4
    • 0344951184 scopus 로고    scopus 로고
    • Metropolis: An integrated electronic system design environment
    • Claudio.passerone@polito.it lavagno@polito.it harry@cs.ucr.edu watanabe@cadence.com felice@cadence.com alberto@eecs.berkeley.edu
    • F. Balarin felice@cadence.com Y. Watanabe watanabe@cadence.com H. Hsieh harry@cs.ucr.edu L. Lavagno lavagno@polito.it C. Passerone Claudio. passerone@polito.it A. Sangiovanni-Vincentelli alberto@eecs.berkeley.edu Metropolis: an integrated electronic system design environment. Computer 36 4 2003 45 52
    • (2003) Computer , vol.36 , Issue.4 , pp. 45-52
    • Balarin, F.1    Watanabe, Y.2    Hsieh, H.3    Lavagno, L.4    Passerone, C.5    Sangiovanni-Vincentelli, A.6
  • 8
  • 12
    • 33744752126 scopus 로고    scopus 로고
    • Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design
    • cerav@poms.ucl.ac.be cagkan@science.uva.nl andy@science.uva.nl
    • C. Erbas cagkan@science.uva.nl S. Cerav-Erbas cerav@poms.ucl.ac.be A. D. Pimentel andy@science.uva.nl Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design. IEEE Transactions on Evolutionary Computation 10 3 2006 358 374
    • (2006) IEEE Transactions on Evolutionary Computation , vol.10 , Issue.3 , pp. 358-374
    • Erbas, C.1    Cerav-Erbas, S.2    Pimentel, A.D.3
  • 16
    • 0038675299 scopus 로고    scopus 로고
    • A software framework for efficient system-level performance evaluation of embedded systems
    • jcofflan@science.uva.nl andy@science.uva.nl Melbourne, Fla, USA
    • J. E. Coffland jcofflan@science.uva.nl A. D. Pimentel andy@science.uva.nl A software framework for efficient system-level performance evaluation of embedded systems. Proceedings of the ACM Symposium on Applied Computing Melbourne, Fla, USA 2003 666 671
    • (2003) Proceedings of the ACM Symposium on Applied Computing , pp. 666-671
    • Coffland, J.E.1    Pimentel, A.D.2
  • 22
    • 26444566457 scopus 로고    scopus 로고
    • The artemis workbench for system-level performance evaluation of embedded systems
    • A. D. Pimentel The artemis workbench for system-level performance evaluation of embedded systems. International Journal of Embedded Systems 1 2005 7
    • (2005) International Journal of Embedded Systems , vol.1 , Issue.7
    • Pimentel, A.D.1
  • 23
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    • Developing architectural platforms: A disciplined approach
    • kulkarni@ic.eecs.berkeley.edu
    • A. Mihal C. Kulkarni kulkarni@ic.eecs.berkeley.edu C. Sauer Developing architectural platforms: a disciplined approach. IEEE Design and Test of Computers 19 6 2002 6 16
    • (2002) IEEE Design and Test of Computers , vol.19 , Issue.6 , pp. 6-16
    • Mihal, A.1    Kulkarni, C.2    Sauer, C.3
  • 24
    • 84949452922 scopus 로고    scopus 로고
    • Rapid system-level performance evaluation and optimization for application mapping onto SoC architectures
    • Rochester, NY, USA
    • S. Mohanty V. K. Prasanna Rapid system-level performance evaluation and optimization for application mapping onto SoC architectures. Proceedings of the 15th Annual IEEE International ASIC/SOC Conference Rochester, NY, USA 2002 160 167
    • (2002) Proceedings of the 15th Annual IEEE International ASIC/SOC Conference , pp. 160-167
    • Mohanty, S.1    Prasanna, V.K.2
  • 26
    • 9644281035 scopus 로고    scopus 로고
    • Methods for evaluating and covering the design space during early design development
    • gries@computer.org
    • M. Gries gries@computer.org Methods for evaluating and covering the design space during early design development. Integration, the VLSI Journal 38 2 2004 131 183
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    • Gries, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.