Efficient memory utilization on network processors for deep packet inspection

ANCS 2006 - Proceedings of the 2006 ACM/IEEE Symposium on Architectures for Networking and Communications Systems

Volumn , Issue , 2006, Pages 71-80

  Piyachon, Piti ^a   Luo, Yan ^a  

^a University of Massachusetts   (United States)

Author keywords

Deep packet inspection; Network processor; Parallel processing; Pattern matching

Indexed keywords

ALGORITHMS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; PARALLEL PROCESSING SYSTEMS; PATTERN MATCHING; SIMULATORS;

DEEP PACKET INSPECTION; MEMORY UTILIZATION; NETWORK PROCESSORS; PROGRAMMABILITY;

PACKET NETWORKS;

EID: 34547683817     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1185347.1185358     Document Type: Conference Paper

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