An efficient hardware interleaver for 3G turbo decoding

Proceedings - 2003 IEEE Radio and Wireless Conference, RAWCON 2003

Volumn , Issue , 2003, Pages 199-201

  Ampadu, P ^a   Kornegay, K ^a  

^a Cornell Broadband Commun Res Labs ^*  (United States)

Author keywords

Broadband communication; Counting circuits; Hardware; Interleaved codes; Iterative algorithms; Iterative decoding; Registers; Signal generators; Signal processing; Turbo codes

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTER HARDWARE; COUNTING CIRCUITS; ENERGY EFFICIENCY; HARDWARE; ITERATIVE METHODS; SIGNAL GENERATORS; SIGNAL PROCESSING; TURBO CODES;

ADDRESS COMPUTATION; BROADBAND COMMUNICATION; HARDWARE INTERLEAVER; INTERLEAVED CODES; ITERATIVE ALGORITHM; PROGRAMMABLE PROCESSORS; REGISTERS; VLSI IMPLEMENTATION;

ITERATIVE DECODING;

EID: 34547572306     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RAWCON.2003.1227927     Document Type: Conference Paper

References (2)

1. 3rd Generation Partnership Project (3GPP) TSG-RAN: "Multiplexing and Channel Coding," Release 4, Version 4.2.0, Sept. 2001. Document available at www.3gpp.org.
2. C. Berrou, A. Glavieux, and P. Thitimajshima, "Near-Shannon Limit Error-Correcting Coding and Decoding: Turbo Codes," Proc. 1993 IEEE Int. Comm. Conf. (Geneva, Switzerland, May 1993), pp. 1064-1070.