-
1
-
-
0036704299
-
Energy-Centric Enabling Technologies For Wireless Sensor Networks
-
August
-
R. Min et al, "Energy-Centric Enabling Technologies For Wireless Sensor Networks", IEEE Wireless Communications, 9(4), August 2002.
-
(2002)
IEEE Wireless Communications
, vol.9
, Issue.4
-
-
Min, R.1
-
2
-
-
0034230287
-
Dual-threshold voltage techniques for low-power digital circuits
-
July
-
J.T. Kao and A. Chandrakasan, "Dual-threshold voltage techniques for low-power digital circuits," IEEE JSSC, 35(7), July 2000.
-
(2000)
IEEE JSSC
, vol.35
, Issue.7
-
-
Kao, J.T.1
Chandrakasan, A.2
-
3
-
-
0029359285
-
1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS
-
August
-
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS, " IEEE JSSC, 30(8), August 1995.
-
(1995)
IEEE JSSC
, vol.30
, Issue.8
-
-
Mutoh, S.1
Douseki, T.2
Matsuya, Y.3
Aoki, T.4
Shigematsu, S.5
Yamada, J.6
-
4
-
-
1442311893
-
Composite ULP diode fabrication, modeling and applications in multi-Vth FD SOI CMOS technology
-
D. Levacq, C. Liber, V. Dessard and D. Flandre, "Composite ULP diode fabrication, modeling and applications in multi-Vth FD SOI CMOS technology," in Solid State Electronics, 48(6), 2004.
-
(2004)
Solid State Electronics
, vol.48
, Issue.6
-
-
Levacq, D.1
Liber, C.2
Dessard, V.3
Flandre, D.4
-
5
-
-
0142185899
-
Ultra Low-Power design techniques using special SOI MOS diodes
-
Newport Beach, USA, September 29, October 2nd
-
D. Levacq, C. Liber, V. Dessard and D. Flandre, "Ultra Low-Power design techniques using special SOI MOS diodes," Proc. of the 2003 IEEE Int. SOI Conf., Newport Beach, USA, September 29 - October 2nd, 2003.
-
(2003)
Proc. of the 2003 IEEE Int. SOI Conf
-
-
Levacq, D.1
Liber, C.2
Dessard, V.3
Flandre, D.4
-
7
-
-
0015718497
-
Clocked CMOS calculator circuitry
-
Y. Suzuki, K. Odagawa and T. Abe, "Clocked CMOS calculator circuitry", IEEE JSSC, 8(6), 1973.
-
(1973)
IEEE JSSC
, vol.8
, Issue.6
-
-
Suzuki, Y.1
Odagawa, K.2
Abe, T.3
-
8
-
-
0034293891
-
A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current
-
October
-
H. Kawaguchi, K. Nose and T. Sakurai, "A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current",IEEE JSSC, 35(10), October 2000.
-
(2000)
IEEE JSSC
, vol.35
, Issue.10
-
-
Kawaguchi, H.1
Nose, K.2
Sakurai, T.3
-
9
-
-
0033116422
-
Comparative Analysis of Master- Slave Latches and Flip-Flops for High-Performance and Low-Power Systems
-
April
-
V. Stojanovic and V.G. Oklobdzija, "Comparative Analysis of Master- Slave Latches and Flip-Flops for High-Performance and Low-Power Systems," IEEE JSSC, 34(4), April 1999.
-
(1999)
IEEE JSSC
, vol.34
, Issue.4
-
-
Stojanovic, V.1
Oklobdzija, V.G.2
|