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Volumn 2268, Issue , 2002, Pages 89-111

Translating imperative affine nested loop programs into process networks

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; NETWORK ARCHITECTURE; SIGNAL PROCESSING; SPECIFICATIONS; STRUCTURED PROGRAMMING;

EID: 34547424838     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45874-3_6     Document Type: Conference Paper
Times cited : (7)

References (17)
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    • Special Issue on Hardware/Software Co-Design. In Proceedings of the IEEE, Mar. 1997.
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  • 2
    • 84949223188 scopus 로고    scopus 로고
    • A Methodology to Design Programmable Embedded Systems
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    • B. Kienhuis et al.: A Methodology to Design Programmable Embedded Systems. In Lecture Notes in Computer Science, this Volume.
    • Lecture Notes in Computer Science
    • Kienhuis, B.1
  • 3
    • 84949224371 scopus 로고    scopus 로고
    • An Overview of Methodologies and Tools in the Field of System-level Design
    • this Volume
    • V. Zivkovic, P. Lieverse: An Overview of Methodologies and Tools in the Field of System-level Design. In Lecture Notes in Computer Science, this Volume.
    • Lecture Notes in Computer Science
    • Zivkovic, V.1    Lieverse, P.2
  • 4
    • 0031097394 scopus 로고    scopus 로고
    • Design of Embedded Systems: Formal Models, Validation, and Synthesis
    • Mar
    • S. Edwards et al.: Design of Embedded Systems: Formal Models, Validation, and Synthesis. In Proceedings of the IEEE, pp. 366-390, Mar. 1997.
    • (1997) Proceedings of the IEEE , pp. 366-390
    • Edwards, S.1
  • 5
    • 0000404969 scopus 로고    scopus 로고
    • A methodology for architecture exploration of heterogeneous signal processing systems
    • Nov
    • P. Lieverse et al.: A methodology for architecture exploration of heterogeneous signal processing systems. In Journal of VLSI Signal Processing, Vol. 29, No. 3, pp. 197-207, Nov. 2001.
    • (2001) Journal of VLSI Signal Processing , vol.29 , Issue.3 , pp. 197-207
    • Lieverse, P.1
  • 7
    • 84949275648 scopus 로고
    • Div, Floor, Ceil, Mod and Step Functions in Nested Loop Programs and Linearly Bounded Lattices
    • M. Moonen and F. Catthoor (eds.), Kluwer
    • P. Held, B. Kienhuis: Div, Floor, Ceil, Mod and Step Functions in Nested Loop Programs and Linearly Bounded Lattices. In Algorithms and Parallel Vlsi Architectures III, M. Moonen and F. Catthoor (eds.), pp. 271-282, Kluwer, 1995.
    • (1995) Algorithms and Parallel Vlsi Architectures III , pp. 271-282
    • Held, P.1    Kienhuis, B.2
  • 8
    • 0038501151 scopus 로고
    • Compiling for massively parallel architectures: A perspective
    • M. Moonen and F. Catthoor (eds.), Kluwer
    • F. Feautrier: Compiling for massively parallel architectures: A perspective. In Algorithms and Parallel VLSI Architectures III, M. Moonen and F. Catthoor (eds.), pp. 259-270, Kluwer, 1995.
    • (1995) Algorithms and Parallel VLSI Architectures III , pp. 259-270
    • Feautrier, F.1
  • 9
    • 0034197210 scopus 로고    scopus 로고
    • Deriving Process Networks from Nested Loop Algorithms
    • E. Rijpkema: Deriving Process Networks from Nested Loop Algorithms. In Parallel Processing Letters, Vol. 10, Nos. 2 & 3, pp. 165-176, 2000.
    • (2000) Parallel Processing Letters , vol.10 , Issue.2-3 , pp. 165-176
    • Rijpkema, E.1
  • 12
    • 0002600143 scopus 로고
    • Sur les polyédres rationnels homothétiques á n dimsions
    • Paris
    • 12.E. Ehrhart: Sur les polyédres rationnels homothétiques á n dimsions. In C.R. Acad. Sci. Paris, Vol. 254, pp. 616-618, 1962.
    • (1962) C.R. Acad. Sci , vol.254 , pp. 616-618
    • Ehrhart, E.1
  • 17
    • 84949233749 scopus 로고    scopus 로고
    • System Level Design with Spade: An M-JPEG Case study
    • San Jose
    • T. Stefanov et al.: System Level Design with Spade: an M-JPEG Case study. In Proceedings Int. Conf. on Computer Aided Design, pp. 384-388, San Jose, 2001.
    • (2001) Proceedings Int. Conf. On Computer Aided Design , pp. 384-388
    • Stefanov, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.