An interleaver implementation for the serially concatenated pulse-position modulation decoder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 4244-4247

  Cheng, Michael K ^a   Moision, Bruce E ^a   Hamkins, Jon ^a   Nakashima, Michael A ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEINTERLEAVER ARCHITECTURES; INTERLEAVER IMPLEMENTATION; PULSE-POSITION MODULATION DECODER;

BANDWIDTH; DECODING; ERROR CORRECTION; NASA; TURBO CODES;

PULSE WIDTH MODULATION;

EID: 34547372300     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. M. Cheng, M. Nakashima, J. Hamkins, B. Moision, and M. Barsoum, "A field-programmable gate array implementation of the serially concatenated pulse-position modulation decoder," JPL Interplanetary Network Progress Report, vol. 42-161S, May 2005.
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5. J. Sun and O. Y. Takeshita, "Interleavers for turbo codes using permutation polynomials over integer rings," IEEE Trans. Inform. Theory, vol. 51, pp. 101-119, Jan. 2005.
6. R. Akella and J. K. Wolf, "On the parallel MAP algorithm," in IEEE fourth workshop on multimedia signal processing, pp. 371-376, IEEE, Oct. 2001.