Off-chip decoupling capacitor allocation for chip package co-design

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 618-621

  Yu, Hao ^a   Chu, Nta ^b   He, Lei ^b  

^a Berkeley DA Inc   (United States)

^b University of California   (United States)

Author keywords

Model order reduction; PG grid simulation

Indexed keywords

MACROMODELING; MODEL ORDER REDUCTION; PG GRID SIMULATION; POWER INTEGRTY TARGET;

CAPACITORS; CIRCUIT SIMULATION; INPUT OUTPUT PROGRAMS; INTEGRATED CIRCUIT LAYOUT;

CHIP SCALE PACKAGES;

EID: 34547343645     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375237     Document Type: Conference Paper

References (8)

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