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Volumn , Issue , 2006, Pages 389-398

Temporal logics and model checking for fairly correct systems

Author keywords

[No Author keywords available]

Indexed keywords

CONCURRENT ENGINEERING; MODEL CHECKING; PROBABILISTIC LOGICS; SYSTEMS ANALYSIS; TOPOLOGY;

EID: 34547298738     PISSN: 10436871     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LICS.2006.49     Document Type: Conference Paper
Times cited : (14)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.