Realization and optimization of DSP based H.264 encoder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 1921-1924

  Zhe, Wei ^a   Canhui, Cai ^a  

^a HUAQIAO UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; IMAGE CODING; IMAGE COMPRESSION; OPTIMIZATION; REAL TIME SYSTEMS; SCHEDULING; STANDARDS;

REAL-TIME APPLICATIONS; STORAGE RESOURCES; TIME CONSUMING MODULES;

DIGITAL SIGNAL PROCESSING;

EID: 34547297272     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Wiegand T, Sullivan G. H.264 working draft number 2[EB/OL]. 2002-01-29. http://ftp3.itu.int/av-arch/video-site/h26L/jwd2r2.zip.
2. Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 ISO/IEC 14496-10 AVC), 7th Meeting: Pattaya, Thailand, 7-14 March, 2003.
3. TI, TMS320C6414T, TMS320C6415T, TMS320C6416T Fix-Point Digital singal processors [CP/CD]
4. TMS320C6000 Optimizing Compiler User's Guide, Texas Instruments Incorporated, 2002.
5. TMS320C64x DSP Two-Level Internal Memory Reference Guide, Texas Instruments Incorporated, 2004
6. TMS320 DSP/BIOS User's Guide, Texas Instruments Incorporated, 2003.