Use of VPR in design of FPGA architecture

ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Volumn , Issue , 2006, Pages 1880-1882

  Li, Xingzheng ^a,b   Yang, Haigang ^a   Zhong, Hua ^c  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

^b UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

^c BEIJING CITY UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC NETWORK ANALYSIS; ELECTRONIC EQUIPMENT;

GENERIC FPGA; VPR;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34547264427     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2006.306495     Document Type: Conference Paper

References (5)

1. V. Betz and J. Rose, VPR: A New Packing, Placement and Routing Tool for FPGA Research, 1997 International Workshop on Field Programmable Logic and Applications, pp. 213 - 222 (1997).
2. V. Betz, J. Rose and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers (1999).
3. J. L. Kouloheris, A. E. Gama, FPGA Performance versus Cell Granularity, IEEE 1991 Custom Integrated Circuits Conference, pp 6.2.1-6.1.5(1991).
4. Y. Chang, D. F. Wong, and C. K. Wong, Universal Switch Modules for FPGA Design, ACM Trans. On Design Automation of Electronics System, Jan. pp. 80-101 (1996).
5. S. Yang, Logic Synthesis and Optimization Benchmarks, Version 3.0, Tech. Report, Microelectronics Centre of North Carolina (1991).