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Volumn , Issue , 2006, Pages 2773-2776

Neural network Stream Processing core (NnSP) for embedded systems

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; NEURAL NETWORKS; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS;

EID: 34547253173     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (27)

References (12)
  • 6
    • 0037279354 scopus 로고    scopus 로고
    • Implementation issues of neuro-fuzzy hardware: Going toward hw/sw codesign
    • Jan
    • L. M. Reyneri, "Implementation issues of neuro-fuzzy hardware: Going toward hw/sw codesign," IEEE Transactions on Neural Networks, vol. 14, no. 1, pp. 176-194, Jan. 2003.
    • (2003) IEEE Transactions on Neural Networks , vol.14 , Issue.1 , pp. 176-194
    • Reyneri, L.M.1
  • 7
    • 84942426443 scopus 로고    scopus 로고
    • Hardware spiking neural network with run-time reconfigurable conectivity in an autonomous robot
    • Los Alamitos, California
    • D. Roggen, S. Hofmann, Y. Thoma, and D. Floreano, "Hardware spiking neural network with run-time reconfigurable conectivity in an autonomous robot," in Proc. of the 2003 NASA/DoD Conference on Evolvable Hardware, Los Alamitos, California, 2003, pp. 189-198.
    • (2003) Proc. of the 2003 NASA/DoD Conference on Evolvable Hardware , pp. 189-198
    • Roggen, D.1    Hofmann, S.2    Thoma, Y.3    Floreano, D.4
  • 10
    • 0026818499 scopus 로고
    • Hardware requiremnets for neural network pattern classifier, a case study and implementation
    • Feb
    • B. Boser, E. Sackinger, J. Bromley, Y. leCun, and L. Jackel, "Hardware requiremnets for neural network pattern classifier, a case study and implementation," IEEE Micro, vol. 12, no. 1, pp. 32-40, Feb. 1992.
    • (1992) IEEE Micro , vol.12 , Issue.1 , pp. 32-40
    • Boser, B.1    Sackinger, E.2    Bromley, J.3    leCun, Y.4    Jackel, L.5
  • 11
    • 0004322035 scopus 로고
    • K. W. Przytula and V. K. Prasnna, Eds, Englewood Cliffs, New Jersey: Prentice-Hall
    • K. W. Przytula and V. K. Prasnna, Eds., Parallel Digital Implementations of Neural Networks. Englewood Cliffs, New Jersey: Prentice-Hall, 1993.
    • (1993) Parallel Digital Implementations of Neural Networks
  • 12
    • 10944232699 scopus 로고    scopus 로고
    • Trends in design of massively parallel coprocessors implemented in digital ASICs
    • July 25-29
    • P. Foldesy, "Trends in design of massively parallel coprocessors implemented in digital ASICs," in Proc. of the International Joint Conference on Neural Networks (UCNN'04), vol. 4, July 25-29, 2004, pp. 3131-3135.
    • (2004) Proc. of the International Joint Conference on Neural Networks (UCNN'04) , vol.4 , pp. 3131-3135
    • Foldesy, P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.