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Volumn 3312, Issue , 2004, Pages 230-244

Increasing the robustness of bounded model checking by computing lower bounds on the reachable states

Author keywords

[No Author keywords available]

Indexed keywords

BINARY DECISION DIAGRAMS; BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; FORMAL METHODS;

EID: 34547214110     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30494-4_17     Document Type: Article
Times cited : (3)

References (20)
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    • (2002) Fourteenth Conference on Computer Aided Verification (CAV'02) , pp. 151-165
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    • (1996) Eighth Conference on Computer Aided Verification (CAV'96) , pp. 428-432
    • Brayton, R.K.1
  • 4
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    • Graph-based algorithms for Boolean function manipulation
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    • (1986) IEEE Transactions on Computers , vol.C-35 , Issue.8 , pp. 677-691
    • Bryant, R.E.1
  • 5
    • 0028720649 scopus 로고
    • Symbolic exploration of large circuits with enhanced forward/backward traversais
    • Grenoble, France, Sept.
    • G. Cabodi, P. Camurati, and S. Quer. Symbolic exploration of large circuits with enhanced forward/backward traversais. In Proceedings of the Conference on European Design Automation, pages 22-27, Grenoble, France, Sept. 1994.
    • (1994) Proceedings of the Conference on European Design Automation , pp. 22-27
    • Cabodi, G.1    Camurati, P.2    Quer, S.3
  • 7
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    • SAT based abstraction-refinement using ILP and machine learning
    • E. Brinksma and K. G. Larsen, editors, Springer-Verlag, July LNCS 2404
    • E. Clarke, A. Gupta, J. Kukula, and O. Strichman. SAT based abstraction-refinement using ILP and machine learning. In E. Brinksma and K. G. Larsen, editors, Fourteenth Conference on Computer Aided Verification (CAV 2002), pages 265-279. Springer-Verlag, July 2002. LNCS 2404.
    • (2002) Fourteenth Conference on Computer Aided Verification (CAV 2002) , pp. 265-279
    • Clarke, E.1    Gupta, A.2    Kukula, J.3    Strichman, O.4
  • 8
    • 1642580373 scopus 로고    scopus 로고
    • Bounded model checking and induction: From refutation to verification
    • W. A. Hunt, Jr. and F. Somenzi, editors, Springer-Verlag, Boulder, CO, July LNCS 2725
    • L. de Moura, H. Rueß, and M. Sorea. Bounded model checking and induction: From refutation to verification. In W. A. Hunt, Jr. and F. Somenzi, editors, Fifteenth Conference on Computer Aided Verification (CAV'03), pages 1-13. Springer-Verlag, Boulder, CO, July 2003. LNCS 2725.
    • (2003) Fifteenth Conference on Computer Aided Verification (CAV'03) , pp. 1-13
    • De Moura, L.1    Rueß, H.2    Sorea, M.3
  • 9
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    • N. Eén and N. Sörensson. Temporal induction by incremental SAT solving. Electronic Notes in Theoretical Computer Science, 89(4), 2003. First International Workshop on Bounded Model Checking, http://www.elsevier.nl/ locate/entcs/.
    • Electronic Notes in Theoretical Computer Science , vol.89 , Issue.4 , pp. 2003
    • Eén, N.1    Sörensson, N.2
  • 12
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    • Interpolation and SAT-based model checking
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    • K. L. McMillan. Interpolation and SAT-based model checking. In W. A. Hunt, Jr. and F. Somenzi, editors, Fifteenth Conference on Computer Aided Verification (CAV'03), pages 1-13. Springer-Verlag, Berlin, July 2003. LNCS 2725.
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    • M. Sheeran, S. Singh, and G. Stalmarck. Checking safety properties using induction and a SAT-solver. In W. A. Hunt, Jr. and S. D. Johnson, editors, Formal Methods in Computer Aided Design, pages 108-125. Springer-Verlag, Nov. 2000. LNCS 1954.
    • (2000) Formal Methods in Computer Aided Design , pp. 108-125
    • Sheeran, M.1    Singh, S.2    Stalmarck, G.3
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  • 18
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.