Wide Vfband Vth tunability for metal-gated MOS devices with HfLaO gate dielectrics

IEEE Electron Device Letters

Volumn 28, Issue 4, 2007, Pages 258-260

  Wang, X P ^a,b   Yu, H Y ^c   Li, M F ^a,b   Zhu, C X ^a   Biesemans, S ^c   Chin, Albert ^d   Sun, Y Y ^a   Feng, Y P ^a   Lim, Andy ^a   Yeo, Yee Chia ^a   Loh, Wei Yip ^b   Lo, G Q ^b   Kwong, Dim Lee ^b  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c IMEC   (Belgium)

^d NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

CMOS; Fermi level pinning; HfLaO; High k (HK) dielectric; Interfacial dipole; Metal gate (MG); Work function

Indexed keywords

CMOS; FERMI LEVEL PINNING; HFLAO; HIGH-K (HK) DIELECTRIC; INTERFACIAL DIPOLES; METAL GATE (MG); METAL GATE; TUNABILITIES;

DIELECTRIC MATERIALS; ELECTRON MOBILITY; GATES (TRANSISTOR); METALS; MOS DEVICES; PLATINUM; SEMICONDUCTING SILICON; TANTALUM COMPOUNDS; WORK FUNCTION;

GATE DIELECTRICS; CMOS INTEGRATED CIRCUITS;

EID: 34447278109     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.891757     Document Type: Article

References (18)

1. International Technology Roadmap for Semiconductors (ITRS), San Jose, CA: Semiconductor Industry Assoc., 2003.
2. I. De, D. Johri, A. Srivastava, and C. M. Osburn, "Impact of gate workfunction on device performance at the 50 nm technology node," Solid State Electron., vol. 44, no. 6, pp. 1077-1080, Jun. 2000.
3. J. K. Schaeffer, C. Capasso, L. R. C. Fonseca, S. Samavedam, D. C. Gilmer, Y. Liang, S. Kalpat, B. Adetutu, H.-H. Tseng, Y. Shiho, A. Demkov, R. Hegde, W J. Taylor, R. Gregory, J. Jiang, E. Luckowski, M. V. Raymond, K. Moore, D. Triyoso, D. Roan, B. E. White, Jr., and P. J. Tobin, "Challenges for the integration of metal gate electrodes," in IEDM Tech. Dig., 2004, pp. 287-290.
4. V. Narayanan, A. Callegari, F. R. McFeely, K. Nakamura, R Jamison, S. Zafar, E. Cartier, A. Steegen, V. Ku, R Nguyen, K. Milkove, C. Cabral, Jr., M. Gribelyuk, C. Wajda, Y Kawano, D. Lacey, Y Li, E. Sikorski, E. Duch, H. Ng, C. Wann, R. Jammy, M. Ieong, and G. Shahidi, "Dual work function metal gate CMOS using CVD metal electrodes," in VLSI Symp. Tech. Dig., 2004, pp. 192-193.
5. S. Inumiya, Y Akasaka, T. Matsuki, F. Ootsuka, K. Torii, and Y Nara, "A thermally-stable sub-0.9 nm EOT TaSix/HfSiON gate stack with high electron mobility, suitable for gate-first fabrication of hp45 LOP devices," in IEDM Tech. Dig., 2005, pp. 27-30.
6. H. C. Wen, H. N. Alshareef, H. Luan, K. Choi, R Lysaght, H. R. Harris, C. Huffman, G. A. Brown, G. Bersuker, R Zeitzoff, H. Huff, R Majhi, and B. H. Lee, "Systematic investigation of amorphous transition-metalsilicon-nitride electrodes for metal gate CMOS applications," in VLSI Symp. Tech. Dig., 2005, pp. 46-47.
7. 2 gate dielectric," in VLSI Symp. Tech. Dig., 2005, pp. 50-51.
8. 2," in VLSI Symp. Tech. Dig., 2005, pp. 230-231.
9. S. B. Samavedam, L. B. La, R J. Tobin, B. White, C. Hobbs, L. R. C. Fonseca, A. A. Demkov, J. Schaeffer, E. Luckowski, A. Martinez, M. Raymond, D. Triyoso, D. Roan, V Dhandapani, R. Garcia, S. G. H. Anderson, K. Moore, H. H. Tseng, C. Capasso, O. Adetutu, D. C. Gilmer, W J. Taylor, R. Hegde, and J. Grant, "Fermi level pinning with sub-monolayer MeOx and metal gates," in IEDM Tech. Dig., 2003, pp. 307-310.
10. Y.-C. Yeo, T-J. King, and C. Hu, "Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology," J. Appl. Phys., vol. 92, no. 12, pp. 7266-7271, Dec. 2002.
11. H. Y Yu, C. Ren, Y-C. Yeo, J. F. Kang, X. R Wang, H. H. H. Ma, M.-F. Li, D. S. H. Chan, and D.-L. Kwong, "Fermi pinning induced thermal instability of metal gate work functions," IEEE Electron Device Lett., vol. 25, no. 5, pp. 337-339, May 2004.
12. R. Jha, B. Lee, B. Chen, S. Novak, P. Majhi, and V. Misra, "Dependence of PMOS metal work functions on surface conditions of high-K gate dielectrics," in IEDM Tech. Dig., 2005, pp. 47-50.
13. X. R Wang, M.-F. Li, C. Ren, X. F. Yu, C. Shen, H. H. Ma, A. Chin, C. X. Zhu, J. Ning, M. B. Yu, and D.-L. Kwong, "Tuning effective metal gate work function by a novel gate dielectric HfLaO for NMOSFETs," IEEE Electron Device Lett., vol. 27, no. 1, pp. 31-33, Jan. 2006.
14. D. S. Yu, A. Chin, C. C. Laio, C. F. Lee, C. F. Cheng, W. J. Chen, C. X. Zhu, M.-F. Li, W J. Yoo, S. R McAlister, and D. L. Kwong, "3D GOI CMOSFETs with novel IrO2(Hf) Dual Gates and High-k dielectric on 1P6M-0.18 μm-CMOS," in IEDM Tech. Dig., 2004, pp. 181-184.
15. H. Watanabe, N. Ikarashi, and F. Ito, "La-silicate gate dielectrics fabricated by solid phase reaction between La metal and SiO2 underlayers," Appl. Phys. Lett., vol. 83, no. 17, pp. 3546-3548, Oct. 2003.
16. [Online]. Available: http://en.wikipedia.org/wiki/Pauling-scale
17. 2 gate dielectrics and frequency dependency of dynamic BTI in MOSFETs," in IEDM Tech. Dig., 2004, pp. 733-736.
18. X. R Wang, M. F. Li, A. Chin, C. X. Zhu, J. Shao, W Lu, X. C. Shen, X. F. Yu, R. Chi, C. Shen, A. C. H. Huan, J. S. Pan, A. Y Du, R Lo, D. S. H. Chan, and D.-L. Kwong, "Physical and electrical characteristics of high-κ Gate Dielectric Hf(1-x)LaxOy," Solid State Electron., vol. 50, no. 6, pp. 986-991, Jun. 2006.