Anomalous C-V Characteristics of Implanted Poly MOS Structure in n+/p+Dual-Gate CMOS Technology

IEEE Electron Device Letters

Volumn 10, Issue 5, 1989, Pages 192-194

  Hillenius, Steven J ^a   Smith, T E ^a   Manchanda, L ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 34250869424     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.31717     Document Type: Article

References (6)

1. S. J. Hillenius and W. T. Lynch, “Gate material work function considerations for 0.5 micron CMOS,” in Proc. ICCD, 1985, p. 147.
2. S. J. Hillenius et al., “A symmetric submicron CMOS technology,” in IEDM Tech. Dig., 1986, p. 252.
3. J. Y.-C. Sun, Y. Taur, R. H. Dennard, and S. T. Klepner, “Submicrometer-channel CMOS for low-temperature operation,” IEEE Trans. Electron Device, vol. ED-34, no. 1, p. 19, 1987.
4. M. M. Mandurah, K. C. Saraswat, C. R. Helms, and T. I. Kamins, “Dopant segregation in polycrystalline silicon,” J. Appl. Phys., vol. 51, p. 5755, 1980.
5. R. A. Chapman et al., “0.5 micron CMOS for high performance at 3.3 V,” in IEDM Tech. Dig., 1988, pp. 52-55.
6. C. Y. Wong et al., “Doping of N+ and P+polysilicon in a dual-gate CMOS process,” in IEDM Tech. Dig., Dec. 11-14, 1988, pp. 238-241.