Vertical integration: A confederacy of alignment, bonding, and materials technologies

Materials Research Society Symposium Proceedings

Volumn 970, Issue , 2007, Pages 215-223

  Farrens, Shari ^a  

^a SUSS MicroTec Lithography GmbH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIRECT BONDS; INTERSUBSTRATE ALIGNMENT; MATERIALS TECHNOLOGIES; STACKING;

COST EFFECTIVENESS; ELECTRONIC EQUIPMENT MANUFACTURE; ERROR ANALYSIS; FUNCTIONAL ANALYSIS; MEMS;

CMOS INTEGRATED CIRCUITS;

EID: 34250843111     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. N. Moskowitz, "3D Wafer Level Interconnect: The Next Wave of Electronic Packaging", RTI Conference: 3D Architectures for Semiconductor Integration and Packaging, Matthew Mecray, Wilfried Bair, and Bart Swinnen, eds., San Francisco Airport Marriott, Burlingame, CA, Oct. 31-Nov 2, 2006.
2. Y. Kwon, J-Q. Lu, R.J. Gutmann, P.P. Kraft, J.F. McDonald and T.S. Cale, "Wafer bonding Using Low-K Dielectrics as Bonding Glue in Three-Dimensional Integration, The Electrochemical Society, 2001 Joint Meeting, September 2-7, 2001, San Francisco.
3. S. Farrens and J. Hermanowski, "Lights-out MEMS Manufacturing", Adv. Pkg., Aug/Sept 2006, p16-18.