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Volumn , Issue , 2006, Pages 193-196

Reversible wafer bonding; Challenges in ramping up 150mm GaAs wafer production to meet growing demand

Author keywords

150mm GaAs wafer; Backend process; Cycle time reduction; Process capability; Yield

Indexed keywords

CYCLE TIME REDUCTION; FILTRONIC COMPOUND SEMICONDUCTORS; GAAS WAFER; PROCESS CAPABILITIES; PROCESS DEVELOPMENT; SAPPHIRE SUBSTRATES; WAFER BONDING PROCESS; YIELD;

EID: 34250794739     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (13)

References (10)
  • 1
    • 84887488694 scopus 로고    scopus 로고
    • Backside processing
    • April, Heather Knoedler
    • Backside Processing, CS Manufacturing Technology Workshop, April 2005. Heather Knoedler.
    • (2005) CS Manufacturing Technology Workshop
  • 2
    • 33645543951 scopus 로고    scopus 로고
    • A new alternative for temporary wafer mounting
    • April
    • D Mould, and J Moore. 'A New Alternative for Temporary Wafer Mounting.' GaAs ManTech proceedings, pp109-112 April 2002.
    • (2002) GaAs ManTech Proceedings , pp. 109-112
    • Mould, D.1    Moore, J.2
  • 4
    • 84887489104 scopus 로고    scopus 로고
    • Study of reactive ion etching process to fabricate reliable via-hole ground connections in gaas mmics
    • D. S. Rawal, V. R. Agarwal, H. S. Sharma, B. K. Sehgal, R. Gulati and H. P. Vyas, 'Study of Reactive Ion Etching Process to Fabricate Reliable Via-Hole Ground Connections in GaAs MMICs', MANTECH 2004, p.8.18.
    • (2004) MANTECH , pp. 818
    • Rawal, D.S.1    Agarwal, V.R.2    Sharma, H.S.3    Sehgal, B.K.4    Gulati, R.5    Vyas, H.P.6
  • 5
    • 84887429819 scopus 로고    scopus 로고
    • Novel via planarization scheme for high resolution backside wafer processing
    • H. Kazemi, L. Tran, H. Xin, D. Deakin, J. Greer, J. Hacker, 'Novel Via Planarization Scheme for High Resolution Backside Wafer Processing', MANTECH 2004, p.12.6.
    • (2004) MANTECH , pp. 126
    • Kazemi, H.1    Tran, L.2    Xin, H.3    Deakin, D.4    Greer, J.5    Hacker, J.6
  • 6
    • 84887481213 scopus 로고    scopus 로고
    • P backside via formation using high etch rate and low temperature HI-based ICP etching
    • K. Kotani, T. Kawasaki, S. Yaegassi, and H. Yano, 'InP Backside Via Formation Using High Etch Rate and Low Temperature HI-Based ICP Etching', MANTECH 2005, p.97.
    • (2005) MANTECH , pp. 97
    • Kotani, K.1    Kawasaki, T.2    Yaegassi, S.3    Yano, H.4
  • 7
    • 34250889635 scopus 로고    scopus 로고
    • Advances processing of compound semiconductor substrates
    • C. Brubaker, M. Wimplinger, A. Malzer, P. Lindner, 'Advances In Processing of Compound Semiconductor Substrates', MANTECH 2005, p.261.
    • (2005) MANTECH , pp. 261
    • Brubaker, C.1    Wimplinger, M.2    Malzer, A.3    Lindner, P.4
  • 8
    • 84887451569 scopus 로고    scopus 로고
    • Characterization of electrostatic carrier substrates to be used as a support for thin semiconductor wafers
    • K. Bock, C. Landesberger, M. Bleier, D. Bollmann, and D. Hemmetzberger, 'Characterization of electrostatic carrier substrates to be used as a support for thin semiconductor wafers, MANTECH 2005, p.319.
    • (2005) MANTECH , pp. 319
    • Bock, K.1    Landesberger, C.2    Bleier, M.3    Bollmann, D.4    Hemmetzberger, D.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.