A 5-parameter mismatch model for short channel MOS transistors

European Solid-State Circuits Conference

Volumn , Issue , 1999, Pages 440-443

  Serrano Gotarredona, Teresa ^a   Linares Barranco, Bernabé ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

MISMATCH MODELING; MOBILITY DEGRADATION; SATURATION REGION; SHORT CHANNEL TRANSISTORS; STRONG INVERSION REGIONS; TRANSISTOR MISMATCH; TRANSISTOR SIZE; TRANSISTOR TRANSITION;

FIELD EFFECT TRANSISTORS;

TRANSISTORS;

EID: 34250787069     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching Properties of MOS Transistors, " IEEE Journal of Solid-State Circuits, vol. 24, No. 5, pp. 1433-1440, October 1989.
2. J. Bastos, M. Steyaert, A. Pergoot, and W. E. Sansen, "Mismatch Characterization of Submicron MOS Transistors, " Analog Integrated Circuits and Signal Processing, 12, pp. 95-106, Kluwer Academics, February 1997.
3. Y. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1988.
4. U. Cilingiroglu, Systematic Analysis of Bipolar and MOS Transistors. Boston: Artech House, 1993.
5. W H. Press, B. P. Flannery, S. A. Teukolsky, and W. T. Vetterling, Numerical Recipes in C. The Art of Computing. Cambridge University Press, 1988.
6. T. Serrano-Gotarredona and B. Linares-Barranco, "Cheap and Easy Systematic CMOS Transistor Mismatch Characterization, " Proceedings of the 1998 IEEE Int. Symp. on Circuits and Systems (ISCAS'98), Monterrey, June 1998.
7. T. Serrano-Gotarredona and B. Linares-Barranco, "Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation, " Analog Integrated Circuits and Signal Processing, to be published.
8. K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterization and Modeling of Mismatch in MOS Transitors for Precision Analog Design, " IEEE Journal of Solid-State Circuits, vol. SC-21, No. 6, pp. 1057-1066, December 1986.