Combined turbo and convolutional decoder architecture for UMTS wireless applications

Proceedings - 15th Symposium on Integrated Circuits and Systems Design, SBCCI 2002

Volumn , Issue , 2002, Pages 337-342

  Kreiselmaier, G ^a   Vogt, T ^a   Wehn, N ^a   Berens, F ^b  

^a Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); CONVOLUTION; DECODING; MOBILE TELECOMMUNICATION SYSTEMS; RECONFIGURABLE HARDWARE; SYSTEMS ANALYSIS; VLSI CIRCUITS; WIRELESS TELECOMMUNICATION SYSTEMS;

3GPP STANDARD; CHANNEL DECODER; CHANNEL-CODING TECHNIQUES; CONVOLUTIONAL DECODERS; MEMORY RESOURCES; VLSI IMPLEMENTATION; WIRELESS APPLICATION;

CHANNEL CODING;

EID: 34250723938     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2002.1137680     Document Type: Conference Paper

References (12)

1. Y.-N. Chang, H. Suzuki, and K. K. Parhi. A 2-Mb/s 256-State 10-mW Rate-1/3 Viterbi Decoder. IEEE Journal of Solid-State Circuits, 35(6):826-834, June 2000.
2. H. Dawid. Algorithmen und Schaltungsarchitekturen zur Maximum a Posteriori Faltungsdecodierung. PhD thesis, RWTH Aachen, Shaker Verlag, Aachen, Germany, 1996. In German.
3. H. Dawid and H. Meyr. Real-Time Algorithms and VLSI Architectures for Soft Output MAP Convolutional Decoding. In Proc. 1995 International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC '95), pages 193-197, Toronto, Canada, Sept. 1995.
4. O. Joeressen, M. Vaupel, and H. Meyr. High-Speed VLSI Architectures for Soft-Output Viterbi Decoding. VLSI Signal Processing, (8):169-181, 1994.
5. S. S. Pietrobon and A. S. Barbulescu. A Simplification of the Modified Bahl Decoding Algorithm for Systematic Convolutional Codes. In Proc. International Symposium on Information Theory and its Applications, pages 1073-1077, Sydney, Australia, Nov. 1994.
6. P. Robertson, P. Hoeher, and E. Villebrun. Optimal and Sub-Optimal Maximum a Posteriori Algorithms Suitable for Turbo Decoding. European Transactions on Telecommunications (ETT), 8(2):119-125, March-April 1997.
7. P. Robertson, E. Villebrun, and P. Hoeher. A Comparison of Optimal and Sub-Optimal MAP decoding Algorithms Operating in the Log-Domain. In Proc. 1995 International Conference on Communications (ICC '95), pages 1009-1013, Seattle, Washington, USA, June 1995.
8. Third Generation Partnership Project. www.3gpp.org.
9. J. Vogt, K. Koora, A. Finger, and G. Fettweis. Comparison of Different Turbo Decoder Realizations for IMT-2000. In Proc. 1999 Global Telecommunications Conference (Globecom '99), volume 5, pages 2704-2708, Rio de Janeiro, Brazil, Dec. 1999.
10. T. Vogt. VLSI-Implementation of a Reduced-Search MAP-Algorithm. Master's thesis, Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern, 2001.
11. A. Worm. Implementation Issues of Turbo-Decoders. PhD thesis, Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern, Forschungsberichte Mikroelektronik, Bd.3, Germany, 2001.
12. A. Worm, H. Michel, F. Gilbert, G. Kreiselmaier, M. J. Thul, and N. Wehn. Advanced Implementation Issues of Turbo-Decoders. In Proc. 2nd International Symposium on Turbo Codes & Related Topics, pages 351-354, Brest, France, Sept. 2000.