VLSI architecture of low memory and high speed 2-d lifting-based discrete wavelet transform for jpeg2000 applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4554-4557

  Chiang, Jen Shiun ^a   Hsia, Chih Hsien ^a   Chen, Hsin Jung ^a   Lo, Te Jung ^a  

^a TAMKANG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; CMOS TECHNOLOGY; DATA FLOW; HIGH-SPEED OPERATION; JPEG 2000; LIFTING-BASED DISCRETE WAVELET TRANSFORMS; LOSSLESS; LOW MEMORY; MEMORY REQUIREMENTS; PARALLEL SCHEME; PROPOSED ARCHITECTURES; REAL TIME; VLSI ARCHITECTURES; VLSI CHIP; VLSI IMPLEMENTATION;

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; DIGITAL IMAGE STORAGE; PARALLEL ALGORITHMS;

DISCRETE WAVELET TRANSFORMS;

EID: 34250354134     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465645     Document Type: Conference Paper

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