Trench DRAM technologies for the 50nm node and beyond

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2006, Pages 92-93

  Mueller, W ^a   Aichmayr, G ^a   Bergner, W ^a   Goldbach, M ^a   Hecht, T ^a   Kudelka, S ^a   Lau, F ^a   Nuetzel, J ^a   Orth, A ^a   Schloesser, T ^a   Scholz, A ^a   Sieck, A ^a   Spitzer, A ^a   Strasser, M ^a   Wand, P F ^a   Wege, S ^a   Weis, R ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CELL TRANSISTORS; SUPPORT TRANSISTORS;

ASPECT RATIO; CAPACITORS; THREE DIMENSIONAL; TRANSISTORS; VLSI CIRCUITS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 34250333862     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2006.251081     Document Type: Conference Paper

References (11)

1. W.Mueller et al., "Challenges for the DRAM cell scaling to 40nm", IEDM 2005.
2. M.Gutsche et al., "Capacitance enhancement techniques for sub-100nm trench DRAM", IEDM 2001.
3. th ECS Meeting, Denver, May 2006.
4. S.Wege et al., "High aspect ratio deep trench Si etching for technologies below 70nm", SEM-ECS ISTC, March 2005.
5. A.Weber et al., "Data retention analysis on individual cells of 256Mb DRAM in 110nm technology", ESSDERC 2005.
6. H.S.Kim et al., "An outstanding and highly manufacturable 80nm DRAM technology", IEDM 2003.
7. 2 DRAM cell with a double gate vertical transistor for lOOnm and beyond", IEDM 2001.
8. R.Kamatsumata et al., "Fin-array FET on bulk silicon for sub-100nm trench capacitor DRAM", Symp.VlSI Technology 2003.
9. T.Schloesser et al., "Highly scalable sub-50nm vertical double gate trench DRAM cell", IEDM 2004.
10. K.H.Park et al., "Highly scalable Saddle MOSFFT for high density and high performance DRAM", IEEE Trans. Electron Device Letters, Vol. 26, No. 9, September 2005, p.690-692.
11. J.Amon et al., "A highly manufacturable deep trench based DRAM cell layout with planar device in a 70nm technology", IEDM 2004.