An FPGA implementation of high-speed flexible 27-Mbps 8-state turbo decoder

ETRI Journal

Volumn 29, Issue 3, 2007, Pages 363-370

  Choi, Duk Gun ^a,b   Kim, Min Hyuk ^a   Jeong, Jin Hee ^a   Jung, Ji Won ^a   Bae, Jong Tae ^a   Choi, Seok Soon ^a   Yun, Young ^a  

^a Korea Maritime University   (South Korea)

^b STX Engine ^*  (South Korea)

Author keywords

Coset mapping; Dualpath processing; FPGA; Radix 4 algorithm

Indexed keywords

ALGORITHMS; BINARY CODES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PARALLEL PROCESSING SYSTEMS; QUADRATURE PHASE SHIFT KEYING; TURBO CODES;

COSET MAPPING; DECODING SPEED; DUALPATH PROCESSING; RADIX-4 ALGORITHM;

ITERATIVE DECODING;

EID: 34250208735     PISSN: 12256463     EISSN: None     Source Type: Journal    
DOI: 10.4218/etrij.07.0106.0122     Document Type: Article

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