Optimal structural design of multi chip package to reduce the failure in substrate

Key Engineering Materials

Volumn 297-300 II, Issue , 2005, Pages 912-917

  Shin, Dong Kil ^a   Kim, Seung Woo ^a   Kim, Shin ^a   Lee, Seok Won ^a   Choi, Hee Kook ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

FEM analysis; Moir interferometry; Multi chip package; Shadow moir ; Visco elasticity

Indexed keywords

COPPER; FAILURE ANALYSIS; FINITE ELEMENT METHOD; INTERFEROMETRY; STRUCTURAL DESIGN; SUBSTRATES; TENSILE STRESS; VISCOELASTICITY;

MOIRÉ INTERFEROMETRY; MULTI CHIP PACKAGES; SHADOW MOIRÉ;

ELECTRONICS PACKAGING;

EID: 34249706462     PISSN: 10139826     EISSN: 16629795     Source Type: Book Series    
DOI: 10.4028/0-87849-978-4.912     Document Type: Conference Paper

References (4)

1. F.G. Shi and G.P. Li: S. Chungpaiboonpatana, 9th Int'l Symposium on Advanced Packaging Materials (2004), pp. 31
2. M.S. Kiasat, G.Q. Zhang, L.J. Ernst and G. Wisse: Electronic Components and Technology Conference (2001)
3. R.C. Dunne and S.K. Sitaraman: IEEE Tr. on Electronics Packaging manufacturing Vol. 25 (2002), pp. 326
4. D. Post, B.T. Han and P. Ifju: High sensitivity Moire, Springer-Verlag, New York (1994) [5] ABAQUS Users Manual, Ver. 6.4 (2004)