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Volumn 15, Issue 1, 2007, Pages 83-93

Methodology and design flow for assisted neural-model implementations in FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FLOWS; DESIGN TOOL; ERROR PRONES; HIGH-PERFORMANCE PLATFORMS; LOGIC ELEMENTS; MODEL CONSTRUCTION; MODEL IMPLEMENTATION; MODELING APPLICATIONS; NEURAL MODELS; NEW APPROACHES; ON-THE-FLY; PARAMETER CHANGES; POPULATION MODEL; POPULATION SIZES;

EID: 34248597706     PISSN: 15344320     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNSRE.2007.891379     Document Type: Article
Times cited : (36)

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  • 2
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.