Low power data processing system with self-reconfigurable architecture

Journal of Systems Architecture

Volumn 53, Issue 9, 2007, Pages 568-576

  Lorenz, Michael G ^a   Mengibar, Luis ^a   SanMillan, Enrique ^a   Entrena, Luis ^a  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

Author keywords

Digital signal processing; Dynamic partial reconfiguration; FPGAs; Image processing; Low power consumption

Indexed keywords

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSORS; ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE ANALYSIS; MICROPROCESSOR CHIPS;

DATA PROCESSING SYSTEM; DYNAMIC PARTIAL RECONFIGURATION; SELF RECONFIGURABLE ARCHITECTURE;

DATA COMMUNICATION SYSTEMS;

EID: 34248567866     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2006.12.008     Document Type: Article

References (27)

1. Lisa F., Cuadrado F., Rexachs D., and Carrabina J. A reconfigurable coprocessor for a PCI-based real time computer vision system. Field-Programmable Logic and Applications (1997) 392-399
2. J.M. Arnold, D.A. Buell, D.T. Hoang, D.V. Pryor, N. Shirazi, M.R. Thistle, The Splash 2 processor and applications, in: IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD '93. Proceedings 3-6 October, 1993, pp. 482-485.
3. M.J. Wirthling, B.L. Hutchings, A dynamic instruction set computer, in: IEEE Workshop on FPGAs for Custom Computing Machines, April, 1995, pp. 99-107.
4. Hartenstein R. A decade of reconfigurable computing: a visionary retrospective. Design, Automation and Test in Europe (2001) 642-649
5. Compton K., and Hauck S. Reconfigurable computing a survey of system and software. ACM Computing Surveys 34 2 (2002) 171-210
6. Benini L., de Micheli G., and Macii E. Designing low-power circuits: practical recipes. IEEE Circuits and Systems Magazine 1 1 (2001) 6-25
7. Atmel, Configurable Logic: Design and Application Book, San Jose, CA, 1998.
8. J.O. Haenni, J.L. Beuchat, E. Sanchez, RENCO: a reconfigurable network computer, in: Sixth Annual IEEE Symposium on Field-Programmable Custom Computing Machines FCCM'98, 1998.
9. M.A. Aguirre, J. Tombs, A. Torralba, L.G. Franquelo, Experience on VLSI for digital signal processing using advanced FPGAs: the unshades framework, in: 4th European Workshop on Microelectronics Education, 2002, pp. 193-196.
10. C. Carmichael, Configuring Virtex FPGAs from parallel EPROMs with a CPLD, Xilinx Application Note 137, 1999.
11. Khan J., Handa J., and Vemuri R. iPACE-V1 A portable adaptative computing engine for real time applications. Field-Programmable Logic and Applications (2002) 69-78
12. Atmel, AT94K Field programmable system level integrated circuit FPSLIC Data sheet, San Jose, CA, 2002.
13. J. Faura, J.M. Moreno, C. Horton, P.V. Duong, M.A. Aguirre, J.M. Insenser, Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on chip microprocessor, in: Proceedings 7th International Workshop FPL97, September 1997, pp. 1-10.
14. Lysaght P., and Dunlop J. Dynamic reconfiguration of FPGAs. European FPL'93 (1993) 82-94
15. Finc M., and Zemva A. Profiling soft-core processor applications for hardware/software partitioning. Journal of Systems Architecture 51 5 (2005) 315-329
16. Lysaght P., and Subrahmanyam P.A. Guest editor's introduction: advances in configurable computing. IEEE Design & Test of Computers March-April (2005) 85-89
17. DeHon A. The density advantage of Configurable Computing. Computer April (2000) 41-49
18. Huesung K., Somani A.K., and Tyagi A. A reconfigurable multifunction computing cache architecture very large scale integration (VLSI) Systems. IEEE Transactions 9 4 (2001) 509-523
19. A. Derbyshire, W. Luk, Combining serialisation and reconfiguration for convolver designs, in: 8th Annual IEEE Symposium on Field-Programmable Custom Computing Machines FCCM'00, 2000.
20. Omnivision Technologies Inc., OV5510 Data sheet, July 1998.
21. L. Mengibar, M.G. Lorenz, D. Martin, L. Entrena, Experiments in FPGA characterization for low power design, in: XIV Design of Circuits and Integrated Systems Conference, November 1999, pp. 385-390.
22. Naeyuck C., and Kwanho K. Real-time per-cycle energy consumption measurement of digital systems. IEE Electronics Letters 36 13 (2000)
23. C. Barnhart, MIT Cheap Vision Machine, .
24. K. Konolige, SRI Small Vision System, .
25. Texas Instruments, DSP TMS320C62 Datasheet, .
26. Coreco Imaging, MVTools Datasheet, .
27. Matrox Imaging, Matrox Odyssey Xpro Datasheet, .