FiPRe: An implementation model to enable self-reconfigurable applications

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3203, Issue , 2004, Pages 1042-1046

  Möller, Leandro ^a   Calazans, Ney ^a   Moraes, Fernando ^a   Brião, Eduardo ^a   Carvalho, Ewerson ^a   Camozzato, Daniel ^a  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COPROCESSOR; PROGRAM PROCESSORS;

DEDICATED HARDWARE; HARDWARE FUNCTIONALITIES; IMPLEMENTATION MODELS; RECONFIGURABLE COPROCESSORS; RECONFIGURABLE DEVICES; RECONFIGURABLE PROCESSORS; SELF RECONFIGURATION; SELF-RECONFIGURABLE;

RECONFIGURABLE HARDWARE;

EID: 34248553778     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30117-2_123     Document Type: Conference Paper

References (5)

1. F. Barat; R. Lauwereins. Reconfigurable instruction set processors: a survey. In: Rapid System Prototyping (RSP'00), pp.168-173, 2000.
2. D. Robinson; P. Lysaght. Modeling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems using the DCS CAD Framework. In: 9th Field-Programmable Logic and Applications (FPL’99), 1999.
3. J. Henkel. Closing the SoC Design Gap. IEEE Computer, vol 36(9), pp. 119-121, 2003.
4. F. Moraes and N. Calazans. R8 Processor Architecture and Organization Specification and Design Guidelines. 2003. http://www.inf.pucrs.br/~gaph/Projects/R8/public/R8_arq_spec_eng.pdf
5. Xilinx, Inc. Two Flows for Partial Reconfiguration: Module Based or Difference Based. Application Note XAPP290, Version 1.1. 2003.