Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications

Journal of Systems Architecture

Volumn 53, Issue 10, 2007, Pages 703-718

  Ohlendorf, Rainer ^a   Wild, Thomas ^a   Meitinger, Michael ^a   Rauchfuss, Holm ^a   Herkersdorf, Andreas ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

Architecture evaluation and exploration; Network processors; Performance simulation; System on chip

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAM PROCESSORS;

ARCHITECTURE EVALUATION; NETWORK PROCESSORS; PERFORMANCE SIMULATION; SYSTEM-ON-CHIPS;

MICROPROCESSOR CHIPS;

EID: 34248517230     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2007.01.009     Document Type: Article

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