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Volumn , Issue , 2005, Pages 932-935

Hardware realization of fuzzy adaptive filters for non linear channel equalization

Author keywords

channel; communication; equalizers; equipment; FPGA; fuzzy; systems

Indexed keywords

BIT ERROR RATE PERFORMANCE; CHANNEL; FIRST ORDER; FPGA; FUZZY; FUZZY ADAPTIVE FILTERS; GAUSSIAN MEMBERSHIP FUNCTION; HARDWARE IMPLEMENTATIONS; HARDWARE REALIZATION; KEYPOINTS; NONLINEAR CHANNEL; ON-LINE ADAPTATION; PROCESSING SPEED; PROPOSED ARCHITECTURES; REAL TIME; SYSTEMS;

EID: 34248213784     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464742     Document Type: Conference Paper
Times cited : (5)

References (9)
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  • 2
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    • Sarwal, P.1    Srinath, M.2
  • 3
    • 0032119988 scopus 로고    scopus 로고
    • Efficient architecture for Bayesian equalization usinf fuzzy filters
    • Jul
    • S. Patra, B. Mulgrew, "Efficient architecture for Bayesian equalization usinf fuzzy filters", IEEE. Trans. on circuits and systems-II, Vol. 7 No.45, pp. 812-820, Jul. 1998.
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    • Patra, S.1    Mulgrew, B.2
  • 5
    • 0034297774 scopus 로고    scopus 로고
    • Equalization of Nonlinear time-varying channels using type-2 fuzzy adaptive filters
    • Oct
    • Liang, J. Mendel, "Equalization of Nonlinear time-varying channels using type-2 fuzzy adaptive filters", IEEE Trans. on fuzzy systems, Vol. 8 No.5, pp. 551 563, Oct. 2002.
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    • Liang, J.M.1
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  • 9
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    • Xilinx Co., Virtex TM 1.8v Field Programmable Gate Array, production product specification, V2.6.1, June, 2004.
    • Xilinx Co., " Virtex TM 1.8v Field Programmable Gate Array", production product specification, V2.6.1, June, 2004.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.