Due-date assignment for wafer fabrication under demand variate environment

IEEE Transactions on Semiconductor Manufacturing

Volumn 20, Issue 2, 2007, Pages 165-175

  Pearn, W L ^a   Chung, S H ^a   Lai, C M ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Contamination model; Due date assignment; Flow time; Product mix; Wafer fabrication

Indexed keywords

CONTAMINATION; INTEGRATED CIRCUITS; MATHEMATICAL MODELS;

CONTAMINATION MODEL; DUE-DATE ASSIGNMENT; FLOW TIME; PRODUCT MIX; WAFER FABRICATION;

WSI CIRCUITS;

EID: 34248190308     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2007.895215     Document Type: Conference Paper

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