Confirmation of deadlock potentials detected by runtime analysis

Proceeding of the 2006 Workshop on Parallel and Distributed Systems: Testing and Debugging, PADTAD '06

Volumn 2006, Issue , 2006, Pages 41-49

  Bensalem, Saddek ^a   Fernandez, Jean Claude ^a   Havelund, Klaus ^b   Mounier, Laurent ^a  

^a VERIMAG   (France)

^b Kestrel Technology   (United States)

Author keywords

Deadlock detection; Dynamic program analysis; False positives; Java; Multi threading; Scheduler synthesis; Testing

Indexed keywords

COMPUTER SIMULATION; JAVA PROGRAMMING LANGUAGE; MULTITASKING; SCHEDULING; SOFTWARE TESTING;

DEADLOCK DETECTION; DYNAMIC PROGRAM ANALYSIS; FALSE POSITIVES; MULTI-THREADING; RUNTIME ANALYSIS; SCHEDULER SYNTHESIS;

COMPUTER SYSTEM RECOVERY;

EID: 34247512578     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1147403.1147412     Document Type: Conference Paper

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