Novel power transistor design for a process independent high voltage option, in standard CMOS

Proceedings of the International Symposium on Power Semiconductor Devices and ICs

Volumn 2006, Issue , 2006, Pages

  Heringa, A ^a   Sonsky J ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; LOGIC DESIGN;

DEPTH ANALYSIS; INTERLEAVING DRAIN EXTENSIONS; PROCESSING COMPLEXITY;

TRANSISTORS;

EID: 34247488414     PISSN: 10636854     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. J. Šonský and A Heringa: "Dielectric RESURF: Breakdown Voltage Control by STI Layout in Standard CMOS," IEDM2005, December 2005.
2. A.W. Ludikhuize: "A Review of RESURF Technology", ISPSD, pp. 11-18, 2000.