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Volumn 2006, Issue , 2006, Pages 190-201

Circuit lower bounds via ehrenfeucht-fraïssé games

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT LOWER BOUNDS; FIRST ORDER FORMULAS;

EID: 34247484530     PISSN: 10930159     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCC.2006.12     Document Type: Conference Paper
Times cited : (24)

References (9)
  • 5
    • 0002127588 scopus 로고
    • Parity, circuits and the polynomial time hierarchy
    • M. Furst, J. Saxe, and M. Sipser. Parity, circuits and the polynomial time hierarchy. Mathematical Systems Theory, 17:13-27, 1984.
    • (1984) Mathematical Systems Theory , vol.17 , pp. 13-27
    • Furst, M.1    Saxe, J.2    Sipser, M.3
  • 6
    • 0023400985 scopus 로고
    • Languages that capture complexity classes
    • N. Immerman. Languages that capture complexity classes. SIAM J. of Computing, 16(4):760-778, 1987.
    • (1987) SIAM J. of Computing , vol.16 , Issue.4 , pp. 760-778
    • Immerman, N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.