VLSI implementation of greedy-based distributed routing schemes for ad hoc networks

Soft Computing

Volumn 11, Issue 9, 2007, Pages 865-872

  Aloisio, Alberto ^a   Izzo, Vincenzo ^a   Rampone, Salvatore ^b  

^a UNIVERSITY OF NAPLES FEDERICO II   (Italy)

^b UNIVERSITY OF SANNIO   (Italy)

Author keywords

Ad hoc wireless network; FPGA implementation; Greedy algorithm; Minimum set cover

Indexed keywords

DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROBABILITY DISTRIBUTIONS; REAL TIME SYSTEMS; ROUTING ALGORITHMS; VLSI CIRCUITS;

GREEDY ALGORITHMS; MINIMUM SET COVER;

AD HOC NETWORKS;

EID: 34247346842     PISSN: 14327643     EISSN: 14337479     Source Type: Journal    
DOI: 10.1007/s00500-006-0138-7     Document Type: Article

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