New systolic algorithm and array architecture for prime-length discrete sine transform

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 3, 2007, Pages 262-266

  Meher, Pramod Kumar ^a   Swamy, M N S ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b Gina Cody School of Engineering and Computer Science   (Canada)

Author keywords

Discrete cosine transform (DCT); discrete sine transform (DST); systolic array; very large scale integration (VLSI)

Indexed keywords

COMPUTATIONAL COMPLEXITY; DISCRETE COSINE TRANSFORMS; MATHEMATICAL TECHNIQUES; SYSTOLIC ARRAYS;

CYCLIC CONVOLUTION; DISCRETE SINE TRANSFORM (DST); LINEAR SYSTOLIC ARRAY; SYSTOLIC STRUCTURE;

VLSI CIRCUITS;

EID: 34147183660     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.889453     Document Type: Article

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