SRAM cell current in low leakage design

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn 2006, Issue , 2006, Pages 65-70

  Kwai, Ding Ming ^a   Hsiao, Ching Hua ^a,b   Kuo, Chung Ping ^a   Chuang, Chi Hsien ^a   Hsu, Min Chung ^a   Chen, Yi Chun ^a   Sung, Yu Ling ^a   Pan, Hsien Yu ^a   Lee, Chia Hsin ^a   Chang, Meng Fan ^a   Chou, Yung Fa ^a,c  

^a Intellectual Property Library Company   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; THRESHOLD VOLTAGE;

LEAKAGE DESIGNS; LEAKAGE SRAM; LOW VOLTAGE OPERATIONS; THRESHOLD VOLTAGE ADJUSTMENTS;

STATIC RANDOM ACCESS STORAGE;

EID: 34047207083     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2006.28     Document Type: Conference Paper

References (14)

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