What lies between design intent coverage and model checking?

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Das, Sayantan ^a   Basu, Prasenjit ^a   Dasgupta, Pallab ^a   Chakrabarti, P P ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC BREAKDOWN; FORMAL LOGIC; MATHEMATICAL MODELS; MODEL CHECKING;

DESIGN INTENT COVERAGE; FORMAL PROPERTY VERIFICATION; FORMAL VERIFICATION TOOLS; VALIDATION ENGINEERS;

LOGIC DESIGN;

EID: 34047173116     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244051     Document Type: Conference Paper

References (3)

1. ARM AMBA Specification Rev 2.0, http://www.arm.com
2. Clarke, E.M., Grumberg, O., and Peled, D.A., Model Checking, MIT Press, 2000.
3. Das, S., Basu, P., Banerjee, A., Dasgupta, P., Chakrabarti, P.P., Mohan, C.R., Fix, L., Armoni, R., Formal Verification Coverage: Computing the Coverage Gap between Temporal Specifications, In Proc. of ICCAD, San Jose, 198-203, 2004.