Building large networks of biological neurons

Annual International Conference of the IEEE Engineering in Medicine and Biology - Proceedings

Volumn , Issue , 2006, Pages 6548-6551

  Hasler, Paul ^a   Farquhar, Ethan ^b   Gordon, Christal ^c  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF TENNESSEE   (United States)

^c NORTH CAROLINA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIOLOGICAL NEURONS; BIOLOGICAL PHYSICS; BUILDING LARGE NETWORKS; CORTICAL NEURONS;

INTEGRATED CIRCUITS; MATHEMATICAL MODELS; MOSFET DEVICES; NEURAL NETWORKS; POTASSIUM COMPOUNDS; SILANES;

NEURONS;

EID: 34047099859     PISSN: 05891019     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEMBS.2006.260873     Document Type: Conference Paper

References (17)

1. "http://en.wikipedia.org/wiki/pyramidalcells," in Wikipedia, June 2006.
2. C. Mead, Analog VLSI and Neural Systems. Reading, MA: Addison-Wesley, 1989.
3. E. Farquhar and P. Hasler, "A bio-physically inspired silicon neuron," IEEE Transactions on Circuits and Systems 1, 2005.
4. A. Hodgkin and A. Huxley, "The components of membrane conductance in the giant axon of loligo," Journal of Physiology, pp. 497-506, July 1952.
5. M. Mahowald and R. Douglas, "A silicon neuron," Nature, vol. 354, no. 6345, pp. 515-518., 1991.
6. E. R. Kandel, J. H. Schwartz, and T. M. Jessel, Eds., Principles of Neural Science. New York, NY: McGraw-Hill, 2000.
7. D. Johnston and S. Wu, Eds., Foundations of Cellular Neurophysiology. Cambrigde, MA: MIT Press, 1997.
8. M. J. Wall, A. Robert, J. Howe, and M. Usowicz, "The speeding of epsc kinetics during maturation of a central synapse," European Journal of Neuroscience, vol. 15, pp. 785-797, 2002.
9. C. Gordon, E. Farquhar, and P. Hasler, "A family of floating-gate adapting synapse based upon transistor channel models," in Proceedings of the International Symposium on Circuits and Systems, Vancouver, May 2004.
10. P. Hasler, C. Diorio, B. A. Minch, and C. A. Mead, Advances in Neural Information Processing Systems 7. Cambridge, MA: MIT Press, 1995, ch. Single transistor learning synapses, pp. 817-824.
11. R. R. Harrison, J. A. Bragg, P. Hasler, B. A. Minch, and S. Deweerth, "A CMOS programmable analog memory cell array using floating-gate circuits," IEEE Transactions on Circuits and Systems II, vol. 48, no. 1, pp. 4-11, Jan. 2001.
12. M. Kucic, A. Low, P. Hasler, and J. Neff, "A programmable continuous-time floating-gate fourier processor," IEEE Transactions on Circuits and Systems II, vol. 48, no. 1, 2001.
13. P. Hasler, P. D. Smith, D. Graham, R. Ellis, and D. V. Anderson, "Analog floating-gate, on-chip auditory sensing system interfaces," IEEE Transactions on Sensors, 2005.
14. J. Dugger and P. Hasler, "A continuously adapting correlating floating-gate synapse," in Proceedings of the International Symposium on Circuits and Systems, Vancouver, BC, May 2004.
15. T. Hall, C. Twigg, P. Hasler, and D. V. Anderson, "Application performance of elements built in a floating-gate fpaa," in Proceedings of the International Symposium on Circuits and Systems, Vancouver, BC, May 2004.
16. P. Hasler, P. D. Smith, E. Farquhar, and D. V. Anderson, "A neuromoiphic ic connection between cortical dendritic processing and hmm classification," in DSP Workshop, Taos, Aug. 2004.
17. E. Farquhar, C. Gordon, and P. Hasler, "A field programmable neural array," in Proceedings of the International Symposium on Circuits and Systems, Kos, Greece, May 2006.