Chip cooling with integrated carbon nanotube microfin architectures

Applied Physics Letters

Volumn 90, Issue 12, 2007, Pages

  Kordas K ^b   Toth G ^b   Moilanen, P ^b   Kumpumaki M ^b   Vahakangas J ^b   Uusimaki A ^b   Vajtai, R ^a   Ajayan, P M ^b  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

CHIP COOLING; MICROFIN STRUCTURES; NANOTUBE STRUCTURES; SILICON CHIPS;

COOLING; ENERGY DISSIPATION; MULTIWALLED CARBON NANOTUBES (MWCN); SILICON;

MICROPROCESSOR CHIPS;

EID: 33947574948     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.2714281     Document Type: Article

References (19)

1. A. Bar-Cohen and W. M. Rohsenow, ASME J. Heat Transfer 106, 116 (1984).
2. R. E. Simons, V. W. Antonetti, W. Nakayama, and S. Oktay, Heat Transfer in Electronic Packages in Microelectronics Packaging Handbook (Chapman and Hall, New York, 1997), Vol. 1, Chap., p. 314.
3. D. Tuckerman and R. Pease, IEEE Electron Device Lett. 2, 126 (1981).
4. Y. Peles, A. Kosar, C. Mishra, C.-J. Kuo, and B. Schneider, Int. J. Heat Mass Transfer 48, 3615 (2005).
5. M. S. Dresselhaus and P. C. Eklund, Adv. Phys. 49, 705 (2000).
6. M. J. Biercuk, M. C. Llaguno, M. Radosavljevic, J. K. Hyun, A. T. Johnson, and J. E. Fischer, Appl. Phys. Lett. 80, 2767 (2002).
7. Y. Wu, C. H. Liu, H. Huang, and S. S. Fan, Appl. Phys. Lett. 87, 213108 (2005).
8. J. Hone, M. C. Llaguno, M. J. Biercuk, A. T. Johnson, B. Batlogg, Z. Benes, and J. E. Fischer, Appl. Phys. A: Mater. Sci. Process. 74, 339 (2002).
9. M. Zhimin, R. Morjan, J. Anderson, E. E. B. Campbell, and J. Liu, Proceedings of the IEEE 55th Electronic Components and Technology Conference, Lake Buena Vista, FL, 31 May 2005, pp. 51-54.
10. M. Zhimin, J. Anderson, and J. Liu, Proceedings of the IEEE 6th High Density Microsystem Design and Packaging and Component Failure Analysis Conference, Shanghai, China, 30 June 2004, pp. 373-376.
11. A. Y. Cao, V. Veedu, X. S. Li, Z. Yao, M. N. Ghasemi-Nejhad, and P. M. Ajayan, Nat. Mater. 4, 540 (2005).
12. X. S. Li, A. Y. Cao, Y. J. Yung, R. Vajtai, and P. M. Ajayan, Nano Lett. 5, 1997 (2005).
13. S. Talapatra, S. Kar, S. K. Pal, R. Vajtai, L. Ci, P. Victor, M. M. Shaijumon, S. Kaur, O. Nalamasu, and P. M. Ajayan, Nature Nanotechnology 1, 112 (2006).
14. See EPAPS Document No. E-APPLAB-90-021711 for the consecutive steps of device fabrication; soldering the flip chip onto the substrate; usage of solder flux; and finally a block of aligned nanotube structure along its Cr/Cu sputtered side was positioned and soldered on the chip by a fine-placer. This document can be reached via a direct link in the online article's HTML reference section or via the EPAPS homepage (http://www.aip.org/pubservs/epap.html).
15. A. Y. Cao, P. L. Dickrell, W. G. Sawyer, M. N. Ghasemi-Nejhad, and P. M. Ajayan, Science 310, 1307 (2005).
16. L. A. Brignoni and S. V. Garimella, IEEE Trans. Compon., Packag. Manuf. Technol., Part A 22, 399 (1999).
17. P. Kim, L. Shi, A. Majumdar, and P. McEuen, Phys. Rev. Lett. 87, 215502 (2001).
18. S. T. Huxtable, D. G. Cahill, S. Shenogin, L. R. Ozisik, P. Barone, M. Usrey, M. S. Strano, G. Siddons, M. Shim, and P. Keblinski, Nat. Mater. 2, 731 (2003).
19. J. G. Maveety and H. H. Jung, IEEE Trans. Compon. Packag. Technol. 25, 459 (2002).