Sensitivity analysis of coupled interconnects for RFIC applications

IEEE Transactions on Electromagnetic Compatibility

Volumn 48, Issue 4, 2006, Pages 607-612

  Shi, Xiaomeng ^b   Yeo, Kiat Seng ^a,b   Ma, Jian Guo ^a,c   Do, Manh Anh ^a,b   Li, Er Ping ^a,d  

^a IEEE

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA   (China)

^d INSTITUTE OF HIGH PERFORMANCE COMPUTING   (Singapore)

Author keywords

CMOS process; Coupled interconnects; Sensitivity

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; SENSITIVITY ANALYSIS; SILICON;

COUPLED INTERCONNECTS; CROSSTALK CAPACITIES; RFIC APPLICATIONS;

COUPLED CIRCUITS;

EID: 33947241371     PISSN: 00189375     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEMC.2006.884417     Document Type: Article

References (12)

1. X. Shi, J.-G. Ma, K. S. Yeo, M. A. Do, and E. Li, "Equivalent circuit model of on-wafer CMOS interconnects for RFICs," IEEE Trans. Very Large Scale Integr. Syst., vol. 13, no. 9, pp. 1060-1071, Sep. 2005.
2. X. Shi, J.-G. Ma, B. H. Ong, K. S. Yeo, M. A. Do, and E. Li, "Equivalent circuit model of interconnect bends based on S-parameter measurements," Microw: Opt. Technol. Lett., vol. 45, no. 2, pp. 170-173 2005.
3. X. Shi, J.-G. Ma, E. Li, K. S. Yeo, and M. A. Do, "Sensitivity of on-wafer interconnects to CMOS process parameters at radio frequency," in Proc. 16th Int. Zurich Symp. EMC, Zurich, Switzerland, Feb. 2006, pp. 590-594.
4. T. R. Gazizov, "Far-end crosstalk reduction in double-layered dielectric interconnects," IEEE Trans. Etectromagn. Compat., vol. 43, no. 4, pp. 566-572, Nov. 2001.
5. IE3D Manual, I. Zeland Software, 2002.
6. X. Shi, K. S. Yeo, J.-G. Ma, M. A. Do, and E. Li, "Scalable model of on-wafer interconnects for high-speed CMOS ICs," IEEE Trans. Adv. Packag., to be published.
7. J. Zheng, Y. Hahm, V. K. Tripathi, and A. Weisshaar, "CAD-oriented equivalent circuit modeling of on-chip interconnects on lossy silicon substrate," IEEE Trans. Micron: Theory Tech., vol. 48, no. 9, pp. 1443-1451, Sep. 2000.
8. A. Deutsch, P. W. Coteus, G. V. Kopcsay, H. H. Smith, C. W. Surovic, B. L. Krauter, D. C. Edelstein, and P. L. Restle, "On-chip wiring design challenges for gigahertz operation," Proc. IEEE, vol. 89, no. 4, pp. 529-555, Apr. 2001.
9. B. Kleveland, C. H. Diaz, L. Madden, T. H. Lee, and S. S. Wong, "Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and osillator design," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1480-1489, Oct. 2001.
10. Y. Eo, W. R. Eisenstadt, J. Y. Jeong, and O.-K. Kwon, "A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design," IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 129-142, Jan. 2000.
11. B. Kleveland, T. H. Lee, and S. S. Wong, "50-GHz interconnect design in standard silicon technology," in Proc. IEEE MTT-S Int. Microw: Symp. Dig., vol. 3, 1998, pp. 1913-1916.
12. R. H. Havemann and J. A. Hutchby, "High-performance interconnects: An integration overview," Proc. IEEE, vol. 89, no. 5, pp. 586-601, May 2001.