Speeding up VLSI layout verification using fuzzy attributed graphs approach

IEEE Transactions on Fuzzy Systems

Volumn 14, Issue 6, 2006, Pages 728-737

  Zhang, Nian ^a,b   Wunsch II, Donald C ^a,c  

^a IEEE   (United States)

^b South Dakota School of Mines and Technology   (United States)

^c University of Missouri Rolla   (United States)

Author keywords

Fuzzy attributed graph; Fuzzy logic; Very large scale integration (VLSI)

Indexed keywords

FUZZY ATTRIBUTED GRAPH; FUZZY GRAPH MATCHING PROBLEM; TESTING FAULTY CIRCUITS;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; FUZZY SETS; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; MICROELECTRONICS;

VLSI CIRCUITS;

EID: 33947194677     PISSN: 10636706     EISSN: None     Source Type: Journal    
DOI: 10.1109/TFUZZ.2006.877358     Document Type: Article

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