A new simplified multilevel inverter topology for DC-AC conversion

IEEE Transactions on Power Electronics

Volumn 21, Issue 5, 2006, Pages 1311-1319

  Ceglia, Gerardo ^b   Guzmán, Víctor ^a,b   Sánchez, Carlos ^c   Ibáñez, Fernando ^c   Walter, Julio ^b   Giménez, María I ^a,b  

^a IEEE   (Venezuela)

^b UNIVERSIDAD SIMÓN BOLÍVAR   (Venezuela)

^c UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

Capacitor clamped; Diode clamped; Field programmable gate array (FPGA); H bridge; Multilevel inverter

Indexed keywords

CAPACITOR CLAMPED; DIODE CLAMPED; H-BRIDGE; MULTILEVEL INVERTERS;

CAPACITORS; DIODES; ELECTRIC LOSSES; ELECTRIC NETWORK TOPOLOGY; ELECTRIC SWITCHES; PASSIVE NETWORKS;

ELECTRIC INVERTERS;

EID: 33947101348     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2006.880303     Document Type: Article

References (27)

1. J. Rodriguez, J.-S. Lai, and F. Z. Peng, "Multi-level inverter: a survey of topologies, controls, and applications," IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724-738, Aug. 2002.
2. M. Marchesoni and P. Tensa, "Diode-clamped multilevel converters: a practicable way to balance DC-link voltages," IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 752-765, Aug. 2002.
3. Y. Chen, B. Mwinyiwiwa, Z. Wolanski, and B.-T. Ooi, "Unified Power Flow Controller (UPFC) based on chopper stabilized diode-clamped multilevel converters," IEEE Trans. Power Electron., vol. 15, no. 2, pp. 258-267, Mar. 2000.
4. G. Venkataramanan and A. Bendre, "Reciprocity-transpositions-based sinusoidal pulsewidth modulation for diode-clamped multilevel converters," IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1035-1047, Oct. 2002.
5. S. Sirisukprasert, J.-S. Lai, and T.-H. Liu, "Optimum harmonic reduction with a wide range of modulation indexes for multilevel converters," IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 875-881, Aug. 2002.
6. L. M. Tolbert and T. G. Habertier, "Novel multilevel inverter carrier-based PWM method," IEEE Trans. Ind. Appl., vol. 35, no. 5, pp. 1098-1107, Sep./Oct. 1999.
7. X. Yuan and I. Barbi, "A New Diode Clamping Multilevel Inverter," IEEE Trans. Power Electron., vol. 15, no. 4, pp. 711-718, Jul, 2000.
8. M. D. Majrekar, P. K. Steimer, and T. A. Lipo, "Hybrid multilevel power conversion system: a competitive solution for high-power applications," IEEE Trans. Ind. Appl., vol. 36, no. 3, pp. 834-841, May/Jun. 2000.
9. L. M. Tobert, F. Z. Peng, T. Cunnyngham, and J. N. Chiasson, "Charge balance control schemes for cascade multi-level converter in hybrid electric vehicles," IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1058-1064, Oct. 2002.
10. N. P. Schibli, T. Nguyen, and A. C. Rufer, "A three-phase multilevel converter for high-power induction motors," IEEE Trans. Power. Electron., vol. 13, no. 5, pp. 978-986, Sep. 1998.
11. F. Z. Peng, J. W. McKeever, and D. J. Adams, "A power line conditioner using cascade multi-level inverters for distribution systems," IEEE Trans. Ind. Appl., vol. 34, no. 6. pp. 1293-1298, Nov./Dec. 1998.
12. S. Bernet, "Recent developments for high power converter for industry and traction applications," IEEE Trans. Power Electron., vol. 15, no. 6, pp. 1102-1117, Nov. 2000.
13. A. Nagel, S. Bernet, and P. K. Steimer, "A 24 MVA inverter using IGCT series connection for medium voltage applications," in Proc. IEEE IAS Annu. Meeting, Chicago, IL, Oct. 2001, vol. 2, pp. 867-870.
14. E. J. Bueno, R. Garcia, M. Marrón, and F. Espinosa, "Modulation Techniques Comparison for Three Levels VSI Converters," in Proc. IEEE 28th Annu. Conf. Ind. Electron. Soc., Nov. 2002, vol. 2, pp. 908-913.
15. H. du Toit Mouton, "Natural balancing of three-level neutral-point-clamped PWM inverters," IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1017-1025, Oct. 2002.
16. K. Corzine, X. Kou, and J. R. Baker, "Dynamic average- value modeling of four-level drive system," IEEE Trans. Power. Electron., vol. 18, no. 2, pp. 619-627, Oct. 2003.
17. G. Sinha and T. A. Lipo, "A four-level inverter based drive with a passive front end," IEEE Trans. Power Electron., vol. 15, no. 2, pp. 285-294. Mar. 2000.
18. D. E. Soto-Sanchez and T. C. Green, "Voltage balance and control in a multi-level unified power flow controller," IEEE Trans. Power Deliver, vol. 16, no. 4, pp. 732-738, Oct. 2001.
19. T. Ishida, K. Matsuse, K. Sasagawa, and L. Huang, "Fundamental Characteristics of a Five-Level Double Converter for Induction Motor Drives," IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 775-782, Aug. 2002.
20. J. von Bloh and R. W. De Doncker, "Control Strategics for Multilevel Voltage Source Converter for Medium-Voltage DC Transmission Systems," in Proc. 26th Annu. Conf. IEEE Ind. Electron. Soc., Oct. 2000, vol. 2, pp. 1358-1364.
21. Y. Cheng and M. L. Crow, "A Diode-Clamped Multi-Level Inverter for the StatCom/BESS," in Proc. IEEE PES Witter Meeting, Jan. 2002, vol. 1, pp. 470-475.
22. F. Tourkhani, P. Viarouge, and T. A. Meynard, "A simulation-optimization system for the optical design of a multilevel inverter," IEEE Trans. Power Electron., vol. 14, no. 6, pp. 1037-1045, Nov. 1999.
23. K. A. Corzine and X. Kou, "Capacitor voltage balancing in full binary combination schema flying capacitor multilevel inverters," IEEE Power Electron. Lett., vol. 1, no. 1, pp. 2-5, Mar. 2003.
24. C. Sánchez, F. Ib́ñez, M. Alcañiz, J. Polo, and R. Masot, "Analysis of Sigma-Delta modulation techniques in low frequency DC-AC converters," in Proc. IEEE 34th PESC'03, Jun. 2003, pp. 507-512.
25. G. Luckjiff, I. Dobson, and D. Divan, "Interpolative Sigma-Delta modulators for high frequency power electronics applications," in Proc. IEEE PESC95, Atlanta, GA, Jun. 1995, pp. 444-449.
26. J. Yu, M. B. Sandler, and R. E. Hawkin, "Adaptive quantization for one-bit sigma-delta modulation," Proc. Inst. Elect. Eng. G, vol. 139, no. 1, pp. 39-44, Feb. 1992.
27. C. M. Zierhofer, "Adaptive sigma-delta modulation with one-bit quantization," IEEE Trans. Circuits Syst. II, vol. 47, no. 5, pp. 408-415, May 2000.